Designing with Virtex-5 LX, LXT, SXT, FXT, TXT Platform FPGA

Interested in learning how to utilize Virtex™-5 FPGA architectural resources effectively? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.

Topics covered include a Virtex-5 FPGA overview, new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. Additionally, the new resources available in the LXT platform (EMAC, PCI Express, and GTP) are discussed. A combination of modules and labs allow for practical hands-on application of the principles taught.

Note: Please note that the initial course material covers the Virtex-5 LX FPGA platform only. Future revisions will include additional platforms as they become available.

Release Date

Level

FPGA 3

Training Duration

1 day

Who Should Attend?

For those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family.

Prerequisites

• Fundamentals of FPGA Design course
• Designing for Performance course
• Designing with the Virtex-4 Family course or comprehensive knowledge of the Virtex-4 FPGA

Software Tools

• Xilinx ISE® Design Suite: System Edition

Hardware

• Architecture: Virtex-5 FPGA*
• Demo board: None*

* This course focuses on the Virtex-5 architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Describe the 6-input LUT of the Virtex-5 FPGA
• Specify the CLB arrangement in the Virtex-5 FPGA
• Define the block RAM resources of the Virtex-5 FPGA
• Differentiate the arithmetic logic resources of the DSP48E slice in the Virtex-5 FPGA
• Identify the clocking resources of the Virtex-5 FPGA
• Describe the new features of the Virtex-5 LXT FPGA

Course Outline

• Introduction
• Virtex-5 FPGA Overview
• CLB Resources
• Clocking Resources
• Lab 1: Clocking Resources Lab
• I/O Resources
• Memory Resources
• XtremeDSP Technology Resources
• Lab 2: DSP48E Resources Lab
• Virtex-5 LXT FPGA Overview
• Lab 3: (Optional) DSP48E Resources

Lab Descriptions

The labs will provide practical hands-on application of the principles taught throughout the course.

• Lab 1 - Clocking Resources: In this lab, you will use the Architecture Wizard to create a PLL core for instantiation in your design. You will then simulate and verify the PLL core.
• Lab 2 - DSP48E Resources: In this lab, you will create a a MACC and a loadable MACC by using the XtremeDSP™ technology (DSP48E) resource through the CORE Generator™ software. You will then compare the OPMODEs chosen by the CORE Generator software with the expected values.
• Lab 3: DSP48E Resources – The DSP48E resource in the Virtex-5 FPGA can also be utilized to create non-DSP functions in order to save slice resources. In this optional lab, you will create a multiplexer by using the XtremeDSP solution (DSP48E) resource through primitive instantiation. You will then simulate the resources to verify functionality.