Essentials of FPGA Design

Course Description

Use the ISE^® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

This course covers ISE software features, such as the Architecture Wizard, PlanAhead^™ software, PinAhead, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.

For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.

Level

FPGA 2

Training Duration

1 day

Who should attend?

Digital and ASIC designers who are interested in FPGA design training, and have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Recommended RELs

Basic FPGA Architecture: Architecture Wizard and PinAhead

Prerequisites

• Working HDL knowledge (VHDL or Verilog)
• Digital design experience

Other Optional RELs

• Basic HDL Coding Techniques
• Virtex-6 and Spartan-6 FPGA HDL Coding Techniques

Software Tools

Xilinx ISE Design Suite: System Edition

Hardware

• Architecture: Spartan FPGA family*
• Demo board: Spartan demo board*

*This course focuses on the Spartan architecture. Check with your local Authorized Training Provider for the specifics of the in-class board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Take advantage of the primary features of the Xilinx FPGA
• Use the Xilinx Project Navigator to implement and simulate an FPGA design
• Read reports and determine whether your design goals were met
• Use the Architecture Wizard to create DCM instantiations
• Use the PlanAhead tool and PinAhead to make good pin assignments
• Use the Xilinx Constraints Editor to enter global timing constraints

Course Outline

• Course Agenda
• Basic FPGA Architecture
• Xilinx Tool Flow
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Lab 2: Architecture Wizard and PlanAhead Tool
• Lab 3: Pre-Assigning I/O Pins Using PinAhead
• Global Timing Constraints
• Lab 4: Global Timing Constraints
• Synchronous Design Techniques
• Course Summary

Lab Descriptions

• Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Xilinx demo board
• Lab 2: Architecture Wizard and PlanAhead Tool – Use the Architecture Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software
• Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules
• Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint