Fundamentals of FPGA Design

Use th ISE™ software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

This course covers ISE features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints. For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.

Note that one of the prerequisites of Fundamentals of FPGA Design is the completion of the basic FPGA architecture modules listed below. Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.

Level

Fundamental

Training Duration

1 day

Who should attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs.

Prerequisites

• Basic FPGA Architecture: Slice and I/O Resources REL*
• Basic FPGA Architecture: Memory and Clocking REL*
• Basic FPGA Architecture: Architecture Wizard and Floorplan Editor REL
• Working HDL knowledge (VHDL or Verilog)
• Digital design experience

*Recorded e-Learning

Software Tools

Xilinx ISE

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Use Xilinx Project Navigator to implement an FPGA design
• Assign pin locations with the Floorplan Editor tool
• Create DCM instantiations with the Architecture Wizard
• Read reports to determine whether design goals were met
• Use the Constraints Editor to enter basic global timing constraints
• Locate and modify implementation options

Course Outline

• Course Agenda
• Xilinx Tool Flow
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Lab 2: Architecture Wizard and Floorplan Editor Lab
• Lab 3: Pre-Assigning I/O Pins Lab
• Global Timing Constraints
• Lab 4: Global Timing Constraints
• Implementation Options
• Lab 5: Implementation Options
• Synchronous Design Techniques
• Course Summary

Lab Descriptions

• Lab 1 - Xilinx Tool Flow: Create a new project in the ISE Project Navigator and use the Architecture Wizard and he Floorplan Editor in the design process. Implement a design by using default software options. The design will be simulated
• Lab 2 - Architecture Wizard and Floorplan Editor: Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design
• Lab 3 - Pre-Assigning I/O Pins: This lab introduces the basics of making good I/O pin assignments with the Floorplan Editor. Use the SSO Analyzer to avoid ground bounce and the Design Rule Checker to follow the I/O Banking Rules
• Lab 4 - Global Timing Constraints: Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint
• Lab 5 - Implementation Options: Adjust process properties and I/O configuration options to improve the design performance