Designing with the Versal ACAP: PCI Express Systems

Course Description

This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications to improve time to market.The emphasis of this course is on:

  • Describing the Xilinx PCI Express design methodology
  • Enumerating various Xilinx PCI Express core products
  • Selecting the PCI Express IP cores from the Vivado® Design Suite
  • GeneratingPCI Express example designs and simple applications
  • Identifying the advanced capabilities of the PCIe specification

Release Date

January 2021

Level

Connectivity 3

Training Duration

2 days

Who Should Attend?

  • Hardware designers who want to create applications using Xilinx IP cores for PCI Express.
  • Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution.
  • System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications.

Prerequisites

  • Experience with the PCI/PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Some experience with Xilinx implementation tools
  • Some experience with a simulation tool, preferably the Vivado® simulator
  • Moderate digital design experience

Course Outline



  • Introduction to PCI Express
  • Versal ACAP-PCle Solutions Overview
  • Versal ACAP: PCIe Block Architecture and Functionality
  • Versal ACAP: PCIe Block Interfaces Overview
  • Versal ACAP: PCIe Block Requester Interfaces
  • Versal ACAP: PCIe Block Completer Interfaces
  • Versal ACAP: PCIe Block Customization
  • Versal ACAP: PCIe Block Test Bench and Simulation
  • PCIe Block Implementation
  • Versal ACAP-PL PCIe Block Debugging Overview
  • Introduction to DMA
  • PL PCIe XDMA/Bridge Subsystem
  • PL PCle QDMA Subsytem
  • Versal ACAP: CPM4 Architecture and Functionality
  • Versal ACAP: CPM Block Customization
  • Versal ACAP: CPM IP Use Cases
  • Designing with the Versal ACAP PCI Express System Full Course Quiz

Event Schedule

so-logic (top1) (Austria)
  • 03.11. - 04.11.2022 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 06.02. - 07.02.2023 09:00-17:00 — € 1,600.00 excl. VAT Add to cart
  • 15.05. - 16.05.2023 09:00-17:00 — € 1,600.00 excl. VAT Add to cart

Partner

Xilinx
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