Designing with the Zynq UltraScale+ RFSoC
Course Description
This training content is structured to provide designers with an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family. Special emphasis is placed on the Data Converter and Soft-Decision FEC blocks. Power estimation is covered to help designers identify the power demands of the device in various operating modes. Since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device, proper layout and PCB considerations are also covered.
Release Date
December 2018Level
Connectivity 3Training Duration
2 days
Who Should Attend?
Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ RFSoC data converter and SD-FEC hard blocks.Prerequisites
- _Understanding of the Zynq UltraScale+ MPSoC architecture
- Basic familiarity with data converter terms and principles
- Basic familiarity with forward error correction terms and principles
Skills Gained
After completing this comprehensive training, you will know how to:- Describe in general the new Zynq UltraScale+ RFSoC family
- Identify typical applications for the data converters
- Describe the architecture and functionality of the ADC
- Utilize the ADC via configuration, simulation, and implementation
- Describe the architecture and functionality of the DAC
Course Outline
- Workshop Overview
- Zynq UltraScale+ MPSoC Overview
- Zynq UltraScale+ RFSoC Overview
- RFSoC ADC
- RFSoC DAC
- RFSoC Data Converter Design
- PCB Design for RFSoC Devices
- RFSoC SD-FEC
Topic Descriptions
Event Schedule
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