Versal Live Online Workshop


Versal Live Online Workshop Compendium Complete three days - free

To attend the complete three days please click here

Three workshops each one day long, one day each week

Versal Live Online Workshop Compendium 1 : Architecture 2021-09-13 9:00 - 17:00
To attend only Compendium 1 please click here

Versal Live Online Workshop Compendium 2 : High Speed Communication2021-09-20 9:00 -17:00
To attend only Compendium 2 please click here

Versal Live Online Workshop Compendium 3 : AI Engine 2021-09-27 9:00 - 17:00
To attend only Compendium 3 please click here

Sponsored by Xilinx!

Versal Live Online Workshop Compendium 1 : Architecture

  • Reviewing the architecture of the Versal ACAP
  • Describing the different engines available in the Versal architecture and what resources they contain
  • Utilizing the hardened blocks available in the Versal architecture
  • Using the design tools and methodology provided by Xilinx to create complex systems
  • Performing system-level simulation and debugging
Agenda

  • 9:00 - 10:30 Overview Architecture and Sub Families
  • 10:45 - 12:15 Design Flow and Tools (Simulation, Emulation, Debugging, Profiling)
  • 13:00 - 14:30 Processing System PS
  • 14:45 -16:15 Adaptable Engine (Programmable Logic PL)
  • 16:15 Q&A

Versal Live Online Workshop Compendium 2 : High Speed Communication

  • Multigigabit Transceiver MGT
  • High Speed Communication Hard IP
  • Provides a system-level understanding of power and thermal issues related to designing
  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement
Agenda
  • 9:00 - 10:30 Network On Chip NoC Concept
  • 10:45 - 12:15 High Speed Communication (PCIe, GT, CCIX, 100G)
  • 13:00 - 14:30 Memory Hierachy (LUT, BRAM, URAM, OCM, TCM, DDR)
  • 14:45 -16:15 PCB Guidelines (Packages, Thermal Solution, Power Supply)
  • 16:15 Q&A

Versal Live Online Workshop Compendium 3 : AI Engine

  • lllustrating the AI Engine architecture
  • Designing single AI Engine kernels using the Vitis™ unified software platform
  • Designing multiple AI kernels using data flow graphs with the Vitis IDE
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
  • Analyzing and debugging kernel performance
Agenda
  • 9:00 - 10:30 Motivation of AI Engines
  • 10:45 - 12:15 Data types (Scalar and Vector) /li>
  • 13:00 - 14:30 AI Tool Flow
  • 14:45 -16:15 Programming Models
  • 16:15 Q&A
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