• INTRODUCTION
    • Motivation
    • Purpose of this Tutorial
    • Objectives of this Tutorial
    • One Possible Solution for the Modulator Design
    • Creating Modulator IP Core with AXI4 Interface
  • HARDWARE VERIFICATION
    • Introduction to Hardware Verification
    • Mission and Goals of Verification
    • The Verification Cycle
    • Verification Hierarchy
    • Basic Verification Environment - A Test Bench
    • Black Box, White Box and Grey Box Verification
    • Test Benches and Testing Strategies
  • CREATING A DETERMINISTIC TEST BENCH
    • Step 1 - Creating Stimulus Generator Component
      • Simulating a Deterministic Test Bench using Vivado IDE Tool
    • Step 2 - Creating AXI-Lite Protocol Monitor Component
      • Simulating a Deterministic Test Bench using Vivado IDE Tool
    • Step 3 - Creating Internal Register Checker and Scoreboard Component
      • Simulating a Deterministic Test Bench using Vivado IDE Tool
    • Stimululs Definition File (SDF)
      • Detecting Incorrect Implementation of Modulator's Internal Register Map
    • Step 4 - Creating PWM Checker Component
      • Simulating a Deterministic Test Bench using Vivado IDE Tool
    • Step 5 - Creating End of Test Checker Component
      • Simulating a Deterministic Test Bench using Vivado IDE Tool
  • CREATING A RANDOM STIMULUS GENERATION TEST BENCH
    • Deterministic Versus Random Stimulus Generation
    • Creating a Random Stimulus Generation Test Bench
      • Writing a Random Stimulus Generation Test Bench
    • Simulating a Random Stimulus Generation Test Bench using Vivado IDE Tool
      • Creating Modulator Project
      • Creating Modulator Module
      • Adding or Creating Simulation Source Files
      • Simulating with Vivado Simulator
  • MESURING VERIFICATION COVERAGE
    • Overview
      • Structural Coverage
      • Functional Coverage
      • The Right Coverage Analysis Strategy
    • Collecting Functional Coverage
    • Simulating Modulator Design with Coverage Collection
      • Creating Modulator Project
      • Creating Modulator Module
      • Adding or Creating Simulation Source Files
      • Simulating with Vivado Simulator
  • IMPROVING VERIFICATION ENVIRONMENT DEVELOPMENT USING VUNIT
    • Regression Testing using Vunit
      • Basic Concepts of Regression
      • Regression Envirounment for Modulator Design
      • Using VUnit to Develop Regression Envirounment for Modulator Design
    • Testbench Logging using VUnit
      • Levels of Logging
      • Using VUnit for Logging
      • Adding Logging to our Design
      • Running the Tests
    • VUnit Verification Components
      • AXI-Lite Master Verification Component
  • OPEN SOURCE VHDL VERIFICATION METHODOLOGY (OSVVM)
    • Introduction
      • Why VHDL? Why OSVVM?
      • OSVVM Capabilities
      • OSVVM Features
      • Transactions
      • The OSVVM Testbench Framework
      • VHDL Utility Library
      • Scripting Library
      • OSVVM Verification Component Library
      • Benefits of OSVVM
    • Creating Deterministic Tests using OSVVM
      • Getting Started with OSVVM