	All right strictly reserved. Reproduction or issue to third parties, in any form whatsoever, is not permitted without written authority from the proprietors.		VHDL Style Guide

Prepared / Erstellt		Subject Responsible / Verantwortlich	Project Name/Projektname		Page/Seite
Mario Fohler		Peter Thorwartl			of/von 2
Approved / Freigabe		Checked/Geprüft	Date/Datum	Rev.	File/Datei OpenOffice.org Writer
			2008-07-30	1E

1Project Structure

1.1Library

Directory Structure Example

/lib

/vhdl

/msim61f_ise91sp3

/msim62a_ise10sp1

/verilog

/msim62a_ise91sp3

/msim62a_ise10sp1

/pads

/templates

/oo

/lib is the location for project libraries, templates, shared files for multiple projects
/vhdl for vhdl libraries
/verilog for verilog libraries
/pads for layout software symbols, parts, decals
/templates for examples open office

1.2Project Directory

Project Directory Example

project/

/<company_name1>

/<project_name1>

/<project_name2>

/<company_name2>

/<project_name3>

/<project_name4>

<project> is the root of all the projects developed by the company, can be readable for all staff members
<company> company name of the customer
<project-name> is the formal name of the project under development, used also for svn and time table entries

1.3One Project Tree

<project-name>/

info/

/xilinx

/marvell

pcb/

soft/

tools/

upld/

/info additional information form the customer or websites
/pcb schematics and layout files, also production data like gerber and excellon files and searchable PDF of schematic and layout

/upld is the location for the FPGA, CPLD, … data

/soft directory for additional software like drivers
/tools additional tools

/pcb is the location for the layout data

1.4UPLD User Programmable Logic Devices

/upld

/src

/result

/release

/src Everything insight the source directory should be under version control, no binary files
No version numbers in file names under revision control
/result temporary files generated from the tools in subdirectories with the <toolname>\ like ise91sp3, ise82sp3, edk91sp2, msim61f, pads2007, matlab2006b
/release and subdirectory with some kind of design names

automatically generated zip files include src dir report files and programming file ( *.mcs, *.bit, *.elf, *.svf,...) with name of the tag.

src\.

doc\.

figure\.

*.png

*.vsd

html\.

pdf\.

c\.

*.c

*.cpp

*.h

java\*.java

vhdl\*.vhd

verilog\*.v

<toolcompany>\*<toolversion_confname>.*

cmd\

*.make

*.bat

*.sh

1.5File Name

Short but meaningful names
Use only lower case characters
No special character, only alphanumeric and the underscore _ to separate two two substrings are allowed, no spaces.
Name big things first like cpu_register, not register_cpu !
Use only English terms, avoid keywords or commands.
Good names are part of the documentation.
Rename names if the change the functionality
The structure of the file system hierarchy shall mirror the logical structure of the system being modelled. A directory should correspond to one and only one design unit.
Do not use version numbers, if the files are under version control like SVN.