Do not mix between VHDL coding
standards for the whole project.
Use VHDL-93.
Everything (all VHDL keywords
and all user-defined identifier) shall be in lower case.
All user-defined identifiers
shall be meaningful and have words separated by underscores, based
on the English language.
The same identifier name as for
the actual hardware and as in the data sheet.
For signals and variables that
are active low, this shall clearly indicated by their by suffixing n
as in “reset_n”.
Named association shall be used
preferably to positional association.
For objects that are global,
this shall clearly indicate by their suffix “_gc”
Underscores should be used in
literals.
Only literals in base 2, 8, 10,
16 shall be used.
Extended digits in base-16
literals should be in lowercase.
Variable width ports shall be
constrained using generics.
Declarative regions and
blocks shall be indented by four spaces.
Indentation level in sequential
statements shall not exceed 4.
Indented regions in sequential
statements shall not have more than 60 lines.
The TAB character shall not be
used to indent, only use the space character.
Lines should not exceed 120
characters.
Long Lines shall be broken where
there are white spaces.
Line continuations shall be
indented to line-up with the first token at the same nesting level
or by four spaces.
One lines shall separate
concurrent statements and their descriptive comment.
Groups of logically related
statements and declaration shall be separated by one blank line.
Unless otherwise specified,
tokens shall be separated by one space.
No space shall precede a close
parenthesis or semi-colon.
No space should surround a
single quote or dot.
Each statement shall start on a
new line.
Each declaration shall start on
a new line.
Elements in interface
declarations shall be vertical aligned.
Elements in signal, constant
declarations shall be vertical aligned.
Elements in a named association
than span more than one line should be vertical aligned.
Buffer and Linkage ports shall
not be used.
Guarded blocks and guarded
signals should not be used.
Operators shall not be
overloaded lightly.
Attributes ‘range and
‘reverse_range shall be used when scanning arrays.
Enumerates shall be used to
represent non-arithmetic discrete values.
Use too many parentheses, never
let the tool resolve precedence; explicitly declare precedence via
parenthesis.
Use relativ path.
Include only libraries which are
really use in the design!
For interfacing other modules
use only std_logic
and std_logic_vector
as type.
For arithmetic operations use
library ieee.std_logic_signed_bit.all
and
ieee.std_logi0.06"c_signed.all
Use preferred libraries
ieee.std_logic_1164.all,
std.text.all
and std.logic_textio.all
.
