1. VHDL Terms

1.1 Objects

• An object is a named item that has a value of a given type that belongs to a class.

1.2 Classes

• A class is relevant to the nature of the object and represent how the object is used in the model.

1.2.1 Constants

• An object whose value may not be changed.

• Use constants to define data parameters and table lookups.

• Constant shall be used to represent limits and parameters.

• Constant Name: constant_name_c

• Example: (sine_rtl)

...

architecture rtl of sine is

constant sin_ampl_c : vector_t_arr := init_sin_f(depth_g, width_g); -- returns sine amplitude value

signal ampl_cnt_s : integer range 0 to 255 := 0; -- amplitude counter

signal sine_s : std_logic_vector(width_g-1 downto 0) := (others=>'0'); -- sine

begin

...

1.2.2 Signals

• An object with a past history.

• Use signals as channels of communication between concurrent statements (e.g. components, processes).

• Keep the same signal name through different hierarchies. So tracing after signals will be easier.

• Use a prefixes to name the source of this signal, maybe a underscore and the destination of this signal.

• Use a suffix to describe the function of the signal reset, trigger, en,...

• Signal Name: signal_name_s

• Example: see Constants (1.2.1)

1.2.3 Variable

• An object with a single current value.

• Variables shall be used in preference to signals. Signals carry more overheads than variables do. Unless something needs to be seen in another process, use a variable.

• In non-synthesizeable models, avoid using signals to describe storage element. Use variables instead (Signals occupy about two orders more storage than variables during simulation)

• In combinatorial processes read variables then write to them. If variables are written then read, long combinatorial logic and latches will be generated. This come from the fact that variables get their value immediately and not like signals after the process suspends.

• Variable Name: variable_name_v

• Example: (modulator_tb)

...

write_p : process -- write 64 following sin-amplitude values in sin.txt at the work directory (only simulate)

file out_sin_f : text open write_mode is "sin.txt"; -- create file in write mode in work directory

variable out_sin_line_v : line; -- line variable

begin

wait until rising_edge(clk_in_s);

if wr_end_s = '0' and freq_trig_s = '1' then

if wr_count_s = 64 then -- write 64 amplitude values

wr_end_s <= '1'; -- write end/end of file

else

write(out_sin_line_v, dac_amplvalue_s); -- write dac_amplvalue_s value in out_sin_line_v

writeline(out_sin_f, out_sin_line_v); -- write out_sin_line_v in one line of out_sin_f

wr_count_s <= wr_count_s+1; -- increment write counter

end if;

end if;

end process;

...

1.2.4 Files

• An object used to represent file in the host environment

• For portability reasons the only allowed file type is std.textio.text.

• Don’t use absolute path names.

• File Handle Name: file_name_f

• Example: see Variable (1.2.3)

1.3 Types and Subtypes

• Use a package for type definitions, if you use it more then once

• The type of an object represents its structure, composotion and storage requirement (integer, real, std_logic, …) that an object can hold

• Type Name: type_name_t_arr --array

  _rec --record

  _range --range

  _enum --enumeration

• Example: (modulator_pkg)

package modulator_pkg is

type vector_t_arr is array (natural range <>) of integer;

function init_sin_f

(

constant depth_c : in integer;

constant width_c : in integer

)

return vector_t_arr;

end;

package body modulator_pkg is

function init_sin_f

(

depth_c : in integer;

width_c : in integer

)

return vector_t_arr is

variable init_arr_v : vector_t_arr(0 to (2 ** depth_c));

begin

for i in 0 to ((2 ** depth_c) / 2) loop -- calculate positive amplitude values

init_arr_v(i) := integer(round(sin((math_2_pi / real(2 ** depth_c))*

real(i)) * real(2 ** (width_c - 1)))) + integer(2 ** (width_c - 1) - 1);

end loop;

for i in ((2 ** depth_c) / 2 + 1) to (2 ** depth_c) loop -- calculate negativ amplitude values

init_arr_v(i) := integer(round(sin((math_2_pi / real(2 ** depth_c))*

real(i)) * real(2 ** (width_c - 1)))) - integer(2 ** (width_c - 1));

end loop;

return init_arr_v;

end;

end;

1.4 Units

• VHDL contains five design units constructs that can be independently analyzed and stored in a design library.

• Each file shall be named according to the unit it contains.

• A file shall contain only one design unit. This minimizes the amount of recompilation required when a library unit, on which other library depends, is modified.

1.4.1 Libraries

• A library is a collection of compiled design units.

• Example: (modulator_tb)

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_textio.all;

use ieee.std_logic_unsigned.all;

library modelsim_lib;

use modelsim_lib.util.all;

library std;

use std.textio.all;

1.4.2 Entity

• Represent the interface I/O definition and generics.

• Make use of generics for buffer sizes, bus width and all other unit parameters. This provides more readability and reusability of the code.

• Filename: entity_name.vhd

• Example: (dac_ltc2624_rtl.vhd)

entity dac_ltc2624 is

generic(

depth_g : integer range 1 to 99 := 8; -- sine signal 8bit quantized

width_g : integer range 1 to 99 := 12 -- 12 bit sine amplitude value

);

port(

btn_reset : in std_logic; -- reset button

clk_in : in std_logic; -- 50MHz clock

clkdv_in : in std_logic; -- 25MHz clock

dac_clk : out std_logic; -- dac clock

dac_cs_n : out std_logic; -- dac enable

dac_data : out std_logic; -- dac data

dac_reset_n : out std_logic; -- dac reset

freq_trig : in std_logic -- frequency for dac data packages

sine : in std_logic_vector(width_g-1 downto 0) -- frequented sine amplitude

);

end;

1.4.3 Architecture

• Architecture defines how the system behaves. This description can be in different levels of abstraction or different purpose.

• Together the entity/architecture pair represents a component.

• Behavioural beh

• Structural structure

• Register Transfer Level rtl

• Functional fun

• Transaction Level Modeling tlm

• Testbench tb

• Use the company name if it is specific for a company like altera_rtl, xilinx_rtl, lattice_rtl

• Use the family name if it is family specific like xc2vp_rtl,xc9500_rtl

• Filename: entity_name_architecture_name.vhd

• Example: (modulator_rtl.vhd)

architecture rtl of modulator is

...

begin

...

end;

1.4.4 Package

• Provide a collection of declarations (types, constant, signals, component) or subprograms (procedures, functions).

• The subprogram bodies are not described.

• Where possible, packages approved by the IEEE should be used rather than redeveloping similar functionality.

• Packages specific to a particular CAD tool standard should not be used.

• The number of packages used by a model shall not be excessive.

• Filename: package_name_pkg.vhd

• Example: see Types and Subtypes (1.3)

1.4.5 Package Body

• Provide a complete definition of the subprograms.

• Filename: package_name_body.vhd

• Example: see Types and Subtypes (1.3)

1.4.6 Configuration

• Binds a particular architecture to an entity or binds an entity/architecture pair to a component.

• Try to use configuration to map entities and architectures and components in a single file.

• Filename: config_name_cfg.vhd