Schedule

En

First Day

7 Series with Vivado

5 December 2012

Registration 10:00 - 11:00 Track A Track B
Session1 11:00 - 12:15 Vivado Overview High-Level Synthesis
Snacks 12:15 - 13:00
Session2 13:00 - 14:30 Vivado Flow Overview Analog Devices Connectivity
Session3 14:30 - 15:45 Simulation, Floorplanning, IP Packager 7 Series Overview
Break 15:45 - 16:15
Session4 16:15 - 17:30 Constraints Flow and Tcl Scripting Motor Control with Xilinx
Dinner 17:30 - 19:00
Networking 19:00 - open end

Second Day

System Design with Vivado

6 December 2012

Registration 10:00 - 11:00 Track A Track B
Session1 11:00 - 12:15 Embedded Processing Vivado Overview
Snacks 12:15 - 13:00
Session2 13:00 - 14:00 Wireless Communication with focus on SDR Checking the Signal Integrity of Multi-Gigabit-Transceiver
Session3 13:00 - 15:00 Sampling & Processing Real-World Data IP Core Design
Break 15:00 - 15:30
Session4 15:30 - 16:30 High-Speed Serial Communication FPGA System Integration & IBIS-AMI Modeling in SystemVue
Session5 16:30 - 17:30 Designing for Signal and Power Integrity High Level Manufacturing of Electronic Boards
Dinner 17:30 - 19:00
Networking 19:00 - open end

Third Day

Embedded Processing with ZYNQ

7 December 2012

Registration 10:00 - 11:00 Track A Track B
Session1 11:00 - 12:15 Embedded Processing Vivado Overview
Snacks 12:15 - 13:00
Session2 13:00 - 14:00 Exploring Zed Board FPGA Tutorial Courses & FPGA Database
Session3 13:00 - 15:00 Xilinx Strategic Directions Designing for Signal and Power Integrity
Break 15:00 - 15:30
Session4 15:30 - 16:30 Xilinx Industrial & Medical Imaging Software Development
Session5 16:30 - 17:30 High-Level Synthesis Open Linux Courses
Dinner 17:30 - 19:00
Networking 19:00 - open end

For further information please contact us:

email: soopendays2012_org@so-logic.net
Updated at: 2012-11-16 15:07to the top