C-based HLS Coding for Hardware Designers

Course Description

C-based coding is increasingly used for the modeling and high-level synthesis of hardware components. This course provides hardware engineers with sufficient knowledge of C-programming techniques for Vivado™ HLS to take advantage of Xilinx FPGAs. Learn high-level synthesis best practices, methodology, and subtleties of C-based coding for hardware modeling, synthesis, and verification.

Release Date

Sept 2012

Level

DSP 3

Training Duration

1 Day

Who Should Attend?

Hardware engineers looking to utilize high-level synthesis Prerequisites C, C++, or System C knowledge HDL knowledge Hardware design

Software Tools

Vivado System Edition

Hardware

Architecture: Zynq™-7000 All Programmable SoC and 7 series FPGAs

Skills Gained

After completing this comprehensive training, you will know how to:

• Describe the difference between software programming and hardware design
• Model and simulate hardware components using C
• Code hardware components in C for high-level synthesis

Course Outline

• Introduction to Software Design for Hardware Designers
• C-based Algorithmic Coding for Hardware
• Lab 1: High-Level Synthesis of a C Model
• C-based Testbench Coding
• Lab 2: Creating a C-based Testbench for a Simple Hardware Component

Lab Descriptions

• Lab 1: High-Level Synthesis of a C Model – Use various techniques and directives in Vivado HLS to improve design performance. The design under consideration accepts an image in a (custom) RGB format, converts it to the Y’UV color space, and applies a filter to the Y’UV image and converts it back to RGB.
• Lab 2: Creating a C-based Testbench for a Simple Hardware Component – Develop a verification environment used for testing a C-based design and verification in Vivado HLS. The design under consideration is the same design used in the previous lab, a Y’UV filter.