Vivad Design Suite for ISE Software Project Navigator Users

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Course Description

This course offers introductory training on the Vivado™ Design Suite. This course is for experienced ISE® software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.

Release Date

May 2013

Level

FPGA 2

Training Duration

1 Day

Who Should Attend?

Existing Xilinx ISE software Project Navigator FPGA designers

Prerequisites

Recommended Prerequisites

Essential Tcl Scripting for the Vivado Design Suite course

Software Tools

Vivado System Edition

Hardware

  • Architecture: 7 series FPGAs
  • Demo board: Kintex™-7 FPGA KC705 board

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Use the Project Manager to start a new project
  • Identify the Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

Course Outline

  • Design Methodology Summary
  • Vivado IDE Features and Benefits
  • Introduction to the Vivado Design Suite
  • Vivado IDE Project Manager and IP Library
  • Vivado IDE Tool Overview
  • Lab 1: Vivado Tool Overview
  • Vivado IDE Synthesis and Reports
  • Vivado IDE Implementation and Static Timing Analysis
  • Lab 2: Vivado Synthesis and Implementation
  • Appendix: SystemVerilog
  • Appendix: Design Methodology
  • Appendix: HDL Coding Techniques

Lab Descriptions

  • Lab 1: Vivado Tool Overview – Vivado Tool Overview – Create a project in the Vivado Design Suite. Add files, simulate, and elaborate the design. Review the available reports, analyze the design with the Schematic and Hierarchy viewers, and run a design rule check (DRC). Finally, assign some of the I/O pins using the IO Planner.
  • Lab 2: Vivado Synthesis and Implementation – Synthesize and analyze the design with the Schematic viewer, review XDC timing constraints, and run basic static timing analysis using the check_timing and report_clock_utilization reports. Implement the design and analyze some timing critical paths with the Schematic viewer. Download the bitstream to the demonstration board.

Event Schedule

No events found. Event request.

Partner

Xilinx
Updated at: 2013-07-02 13:40to the top