|
22.12. - 22.12.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
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|
20.12. - 21.12.2026 09:00-17:00
|
Developing AI Inference Solutions with the Vitis AI Platform
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
16.12. - 17.12.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
13.12. - 17.12.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
13.12. - 14.12.2026 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
09.12. - 11.12.2026 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
02.12. - 03.12.2026 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
01.12. - 05.12.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
26.11. - 27.11.2026 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
26.11. - 26.11.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
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|
24.11. - 25.11.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
23.11. - 27.11.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
19.11. - 20.11.2026 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
17.11. - 19.11.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
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|
|
13.11. - 14.11.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
11.11. - 12.11.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
10.11. - 14.11.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
08.11. - 12.11.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
06.11. - 07.11.2026 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
04.11. - 05.11.2026 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
03.11. - 07.11.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
28.10. - 29.10.2026 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
28.10. - 29.10.2026 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
27.10. - 28.10.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
22.10. - 24.10.2026 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
22.10. - 26.10.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
21.10. - 22.10.2026 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
15.10. - 16.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
14.10. - 15.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
12.10. - 16.10.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
12.10. - 13.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
08.10. - 09.10.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
07.10. - 09.10.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
06.10. - 07.10.2026 09:00-17:00
|
Designing an Integrated PCI Express System
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
23.09. - 24.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Memory Interfaces
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.09. - 22.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
17.09. - 18.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.09. - 17.09.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.09. - 18.09.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
14.09. - 15.09.2026 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.09. - 10.09.2026 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
07.09. - 11.09.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
04.09. - 05.09.2026 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.09. - 03.09.2026 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
01.09. - 05.09.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
27.08. - 28.08.2026 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
26.08. - 26.08.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
25.08. - 26.08.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
25.08. - 29.08.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
20.08. - 21.08.2026 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
19.08. - 21.08.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
18.08. - 19.08.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
13.08. - 14.08.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.08. - 13.08.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.08. - 15.08.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
06.08. - 07.08.2026 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
05.08. - 06.08.2026 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.08. - 08.08.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
03.08. - 03.08.2026 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
30.07. - 31.07.2026 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
30.07. - 31.07.2026 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.07. - 29.07.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
24.07. - 26.07.2026 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.07. - 26.07.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
21.07. - 22.07.2026 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.07. - 17.07.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
13.07. - 14.07.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.07. - 10.07.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.07. - 10.07.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
07.07. - 08.07.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
06.07. - 10.07.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
02.07. - 04.07.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
01.07. - 02.07.2026 09:00-17:00
|
Designing an Integrated PCI Express System
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
30.06. - 01.07.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
29.06. - 03.07.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
25.06. - 26.06.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
25.06. - 25.06.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
22.06. - 23.06.2026 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
18.06. - 19.06.2026 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.06. - 17.06.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.06. - 16.06.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
10.06. - 14.06.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
09.06. - 10.06.2026 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.06. - 12.06.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
19.05. - 21.05.2026 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
18.05. - 19.05.2026 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.05. - 12.05.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.05. - 08.05.2026 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
07.05. - 11.05.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
06.05. - 07.05.2026 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.05. - 08.05.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
27.04. - 28.04.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Memory Interfaces
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
24.04. - 24.04.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
22.04. - 23.04.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
21.04. - 22.04.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
20.04. - 24.04.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
13.04. - 17.04.2026 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
13.04. - 17.04.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
07.04. - 11.04.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
07.04. - 08.04.2026 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
06.04. - 10.04.2026 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
05.04. - 09.04.2026 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
23.03. - 24.03.2026 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
17.03. - 17.03.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
13.03. - 14.03.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.03. - 13.03.2026 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.03. - 13.03.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
10.03. - 11.03.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.03. - 13.03.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
06.03. - 07.03.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.03. - 05.03.2026 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
03.03. - 04.03.2026 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
02.03. - 06.03.2026 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
27.02. - 03.03.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
24.02. - 25.02.2026 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
23.02. - 27.02.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
18.02. - 19.02.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
18.02. - 19.02.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
18.02. - 19.02.2026 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.02. - 17.02.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.02. - 17.02.2026 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
12.02. - 13.02.2026 09:00-17:00
|
Designing an Integrated PCI Express System
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
10.02. - 11.02.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
10.02. - 14.02.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
10.02. - 10.02.2026 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
05.02. - 06.02.2026 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.02. - 05.02.2026 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
03.02. - 07.02.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
02.02. - 06.02.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
30.01. - 31.01.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Memory Interfaces
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
29.01. - 29.01.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
28.01. - 29.01.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.01. - 29.01.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
26.01. - 27.01.2026 09:00-17:00
|
Developing AI Inference Solutions with the Vitis AI Platform
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
23.01. - 24.01.2026 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.01. - 26.01.2026 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
21.01. - 22.01.2026 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
20.01. - 21.01.2026 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
19.01. - 23.01.2026 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
16.01. - 17.01.2026 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.01. - 19.01.2026 09:00-17:00
|
Design Compendium with SystemC for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
15.01. - 16.01.2026 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.01. - 15.01.2026 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
13.01. - 15.01.2026 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
12.01. - 16.01.2026 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
08.01. - 09.01.2026 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.01. - 09.01.2026 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
05.01. - 05.01.2026 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
23.12. - 24.12.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Memory Interfaces
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.12. - 22.12.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
17.12. - 18.12.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.12. - 17.12.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.12. - 19.12.2025 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
15.12. - 16.12.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.12. - 12.12.2025 09:00-17:00
|
Developing AI Inference Solutions with the Vitis AI Platform
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.12. - 10.12.2025 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.12. - 12.12.2025 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.12. - 05.12.2025 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.12. - 03.12.2025 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
01.12. - 05.12.2025 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
26.11. - 26.11.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
24.11. - 28.11.2025 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
24.11. - 25.11.2025 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
20.11. - 21.11.2025 09:00-17:00
|
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
16.11. - 18.11.2025 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
13.11. - 14.11.2025 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
11.11. - 12.11.2025 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
10.11. - 14.11.2025 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
06.11. - 07.11.2025 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.11. - 05.11.2025 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
03.11. - 07.11.2025 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
30.10. - 31.10.2025 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
30.10. - 31.10.2025 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.10. - 29.10.2025 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
27.10. - 31.10.2025 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
27.10. - 29.10.2025 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
21.10. - 22.10.2025 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
20.10. - 24.10.2025 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
16.10. - 17.10.2025 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
14.10. - 15.10.2025 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
13.10. - 17.10.2025 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,259.00
|
Add to cart
|
|
09.10. - 10.10.2025 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
07.10. - 08.10.2025 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
06.10. - 08.10.2025 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
Add to cart
|
|
02.10. - 03.10.2025 09:00-17:00
|
Designing an Integrated PCI Express System
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
30.09. - 01.10.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
29.09. - 29.09.2025 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
25.09. - 26.09.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Power and Board Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
23.09. - 24.09.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Memory Interfaces
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
22.09. - 26.09.2025 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
22.09. - 22.09.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
Add to cart
|
|
20.09. - 21.09.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
17.09. - 18.09.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Hardware Debug
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
15.09. - 19.09.2025 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
11.09. - 12.09.2025 09:00-17:00
|
Developing AI Inference Solutions with the Vitis AI Platform
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
09.09. - 13.09.2025 09:00-17:00
|
Design Compendium with SystemC for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
09.09. - 10.09.2025 09:00-17:00
|
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
08.09. - 12.09.2025 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
04.09. - 05.09.2025 09:00-17:00
|
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
02.09. - 03.09.2025 09:00-17:00
|
Designing with Versal AI Engine: Architecture and Design Flow - 1
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
01.09. - 05.09.2025 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
28.08. - 29.08.2025 09:00-17:00
|
Designing with Ethernet MAC Controllers
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Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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27.08. - 27.08.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 850.00
|
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25.08. - 26.08.2025 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
25.08. - 29.08.2025 09:00-17:00
|
Design Compendium with Verilog for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
22.08. - 23.08.2025 09:00-17:00
|
High-Level Synthesis with the Vitis Unified IDE (HLS)
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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21.08. - 22.08.2025 09:00-17:00
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DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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18.08. - 19.08.2025 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
18.08. - 20.08.2025 09:00-17:00
|
Design Compendium with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 2,550.00
|
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|
14.08. - 15.08.2025 09:00-17:00
|
Embedded Design with PetaLinux Tools
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
12.08. - 13.08.2025 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
11.08. - 15.08.2025 09:00-17:00
|
Design Compendium Embedded System for AMD XIlinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
07.08. - 08.08.2025 09:00-17:00
|
Operating Systems and Hypervisors in Adaptive SoCs
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
05.08. - 06.08.2025 09:00-17:00
|
Embedded Heterogeneous Design
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
04.08. - 08.08.2025 09:00-17:00
|
Design Compendium with High Level Synthesis for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
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|
|
31.07. - 01.08.2025 09:00-17:00
|
Verification with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
28.07. - 30.07.2025 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
28.07. - 29.07.2025 09:00-17:00
|
Designing with SystemVerilog
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
Add to cart
|
|
28.07. - 01.08.2025 09:00-17:00
|
Design Compendium Verification with VHDL for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
|
27.07. - 28.07.2025 09:00-17:00
|
Vitis Model Composer: A MATLAB and Simulink-based Product
|
Xilinx
|
Virtual Learning Environment (Online)
|
€ 1,700.00
|
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|
|
21.07. - 25.07.2025 09:00-17:00
|
Design Compendium Yocto for AMD Xilinx devices
|
so-logic
|
Virtual Learning Environment (Online)
|
€ 4,250.00
|
Add to cart
|
