How to Design a High-Speed Memory Interface

Course Description

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs. Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces. The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR, and QDRII+. Labs are available for DDR3 on the Kintex™-7 FPGA KC705 board.

Release Date

November 2012

Level

Connectivity 3

Training Duration

2 days

Who Should Attend?

• FPGA designers and logic designers

Prerequisites

• VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
• Familiarity with logic design: state machines and synchronous design
• Very helpful to have:
• Basic knowledge of FPGA architecture
• Familiarity with Xilinx implementation tools
• Nice to have:
• Familiarity with I/O basics
• Familiarity with high-speed I/O standard

Software Tools

• Xilinx ISE® Design Suite: Logic or System Edition
• Mentor HyperLynx SI

Hardware

• Architecture: Spartan and Virtex FPGA families
• Demo board: Spartan or Virtex demo board

Skills Gained

After completing this comprehensive training, you will know how to:

• Identify the FPGA resources required for memory interfaces
• Describe different types of memories
• Utilize the Xilinx tools to generate memory interface designs
• Simulate memory interfaces with the Xilinx ISim simulator
• Implement memory interfaces
• Identify the board design options for the realization of memory interfaces
• Describe PCB-level simulation
• Test and debug your memory interface design

Course Outline

Day 1

• Introduction
• Spartan and Virtex Family Overview
• Memory Devices
• Spartan FPGA Memory Interfaces
• Virtex FPGA Memory Interfaces
• MIG Design Generation
• Lab 1: MIG Core Generation

Day 2

• MIG Design Simulation
• Lab 2: MIG Design Simulation
• MIG Design Implementation
• Lab 3: MIG Design Implementation
• Memory Interface Board-Level Design
• Memory Interface PCB Simulation
• Lab 4: Signal Integrity Simulation
• Memory Interface Test and Debugging
• Lab 5: MIG Design Debugging

Lab Descriptions

• Lab 1: MIG Core Generation – Create a DDR2 or DDR3 memory controller using the Memory Interface Generator (MIG) CORE Generator™ interface. For Spartan devices, customize the hard Memory Controller Block (MCB) targeting the selected Spartan demo board. For Virtex devices, customize the soft core memory controller for the selected Virtex demo board.
• Lab 2: MIG Design Simulation – Simulate the memory controller created in Lab 1 using ISim.
• Lab 3: MIG Design Implementation – Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.
• Lab 4: Signal Integrity Simulation – Evaluate and perform basic verification options available for IBIS simulation of memory interfaces.
• Lab 5: MIG Design Debugging – Debug the memory interface design utilizing the ChipScope Pro™ tool.