Designing with the Versal Adaptive SoC: Network on Chip

This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...

Course Description

This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. It provides an overview of the major components in the Versal device and illustrates how the NoC can be configured to access DDR memory controllers and HBM memory controllers.

The emphasis of this course is on:

• Enumerating the major components comprising the NoC architecture in the Versal adaptive SoC
• Implementing a basic Versal NoC design using the Vivado™ IP integrator
• Accessing the Versal NoC using the modular NoC flow
• Configuring the DDR memory controller for accessing DDR memory
• Configuring and tuning the NoC for efficient data movement

Training Duration

13 hours

Additional Information

• Number of Chapters: 10
• Number of Labs: 5
• Number of Demos: 0
• Current Version: 2025.2

What's New

• Added a new module on NoC DDR5 Memory Controller
• All labs have been updated to the latest software versions

Chapters

Chapter 1

• AMD Versal Adaptive SoC: Architecture Overview for Existing Users

Chapter 2

• AMD Versal Adaptive SoC: NoC Introduction and Concepts

Chapter 3

• AMD Versal Adaptive SoC: NoC Architecture

Chapter 4

• AMD Versal Adaptive SoC: Design Tool Flow – Introduction

Chapter 5

• AMD Versal Adaptive SoC: Modular NoC Flow

Chapter 6

• AMD Versal Adaptive SoC: NoC DDR4 Memory Controller

Chapter 7

• AMD Versal Adaptive SoC: NoC DDR5 Memory Controller

Chapter 8

• AMD Versal Adaptive SoC: NoC HBM Controller

Chapter 9

• AMD Versal Adaptive SoC: NoC Performance Tuning

Chapter 10

• Designing with the Versal Adaptive SoC: Network on Chip Full Course Quiz