Ethernet GMII Core


General Description
Supported FPGA Families and Development Tools
Pricing and Additional Information

General Description

Gigabit media-independent Interface (GMII) is an standard Ethernet interface between Media Access Control (MAC) device and Physical Layer (PHY).

So-Logic's Ethernet GMII core implements GMII interface from the IEEE Std. 802.3-2008 specification.

The interface defines speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit.

The so_ip_eth_gmii core can be evaluated using Xilinx Evaluation Platforms before actual purchase. This is achieved by using a demonstration bit files for KC705 platform that allows the user to connect the So-Logic's complete 1G Ethernet solution system to some other Ethernet enabled device (PC or some Ethernet tester equipment) and evaluate system performance under different transfer scenarios.

For more information about the Ethernet GMII core please consult the corresponding datasheet.


  • Fully compliant with the IEEE Std. 802.3-2008 specification
  • Supports 10/100/1000 Mb/s Ethernet communication speeds
  • Supports GMII interface as defined in IEEE Std. 802.3-2008 specification
  • Low frequency operation
    • IP Core system clocks at 125 MHz for 10/100/1000 Mb/s data rates

Supported FPGA Families and Development Tools

Ethernet GMII core currently supports following Xilinx FPGA device familes:

  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6
  • Spartan-6
  • Virtex-5

Ethernet GMII core currently supports following Xilinx development tools:

  • Xilinx Vivado Design Suite


  • LAN networking
  • Industrial Ethernet
  • Distributed Storage Area Networks
  • Cloud computing


Source code (source code license only)

  • VHDL Source Code

VHDL test bench environment

  • Tests with reference responses

Technical documentation

  • Datasheet
  • Installation notes
  • User manual

Instantiation templates

Example application

Technical support

  • IP Core implementation support
  • Variable length maintenance
  • Delivery of IP Core updates, minor and major changes
  • Delivery of documentation updates
  • Telephone & email support


Netlist License

  • Post-synthesis netlist
  • Self checking testbench
  • Test vectors for testing the core
  • Place&Route scripts
  • Constraints
  • Instantiation templates
  • Documentation

VHDL Source License

  • VHDL RTL source code
  • Complete verification plan together with the functional verification environment to verify the correct operation of the core
  • Self checking testbench
  • Vectors for testing the functionality of the core
  • Simulation & synthesis scripts
  • Documentation



For more information about the So-Logic Ethernet GMII core, please see the following datasheet:

Pricing and Additional Information

Pricing of Ethernet GMII core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the Ethernet GMII core, please contact So-Logic at:

Phone: +43-1-315 77 77-11
Fax: +43-1-315 77 77-44


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