SATA-III Host Controller Core

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Index

General Description
Features
Supported FPGA Families and Development Tools
Applications
Deliverables
Licensing
Documentation
Reference Design and Evaluation Version
Pricing and Additional Information

General Description

The so_ip_sata3_hctrl is a soft core implementation of SATA host controller as defined in the SATA Specification 3.2.

So-Logic's SATA-III Host Controller core is fully compliant with the SATA 3.2 specification, and supports 1.5 Gbit/s, 3.0 Gbit/s and 6.0 Gbit/s data transfer rates.

SATA-III Host Controller core implements physical, link and transport layers. It can use both RocketIO GTP and GTX transceivers found in Xilinx FPGA devices to implement physical signaling required by the SATA specification. For the interface with the host processor IP core uses standard PATA interface, and for the interface with the DMA engine simple TX and RX transaction interface.

SATA-III Host Controller core is delivered with fully automated testbench and a complete set of tests allowing easy package validation at each stage of SoC design flow.

The design of SATA-III Host Controller core is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. It operates at 37.5 MHz system clock frequency in case of SATA-I mode (1.5 Gbit/s data transfer rate), 75 MHz in case of SATA-II mode (3.0 Gbit/s data transfer rate) and at 150 MHz in case of SATA-III mode (6.0 Gbit/s data transfer rate).

SATA-III Host Controller core can be evaluated using Xilinx FPGA Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for Zynq-7000, Artix-7, Kintex-7, Virtax-7, Virtex-6 and Virtex-5 FPGA platforms that allows the user to connect it’s HDD to the SATA core and evaluate system performance under different transfer scenarios.

For more information about the SATA-III Host Controller core please consult the corresponding datasheet.

Features

  • Fully compliant with the Serial ATA specification revision 3.2
  • Simple transaction interface with Host processor and DMA Engine
  • 32-bit internal data path
  • 8 KB FIFO implemented by BlockRAM in both transmit and receive paths
  • Low frequency operation
    • IP Core system clock of 37.5 MHz and PHY clock 75 MHz for SATA-I
    • IP Core system clock of 75.0 MHz and PHY clock 150 MHz for SATA-II
    • IP Core system clock of 150.0 MHz and PHY clock 300 MHz for SATA-III
  • Supports 1.5 Gbit/s, 3.0 Gbit/s and 6.0 Gbit/s data transfer rates
  • Supports DMA and PIO commands
  • Hardware support for
    • Speed auto negotiation for SATA I/II/III
    • 48-bit address set
    • Detection of OOB, COMWAKE, K28.5, etc.
    • 8b/10b coding and decoding
    • CRC generation and checking
    • Auto insertion of HOLD primitives
    • Native Command Queuing (NCQ)
    • Port Multiplier, Port Selector
    • First Party DMA (FPDMA)
  • CONT primitive support for primitive suppression to reduce EMI
  • Implements the shadow register block and the serial ATA status and control registers
  • Supports both Xilinx GTP and GTX RocketIO Transceivers
  • Reference design available on Zynq-7000, Artix-7, Kintex-7, Virtax-7, Virtex-6 and Virtex-5 Xilinx FPGA Evaluation Platfom

Supported FPGA Families and Development Tools

SATA-III Host Controller core currently supports following Xilinx FPGA device familes:

  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-6
  • Virtex-5

SATA-III Host Controller core currently supports following Xilinx development tools:

  • Xilinx ISE Design Suite
  • Xilinx Vivado Design Suite

Applications

  • Hard Disk Drives (HDD)
  • Solid State Drives (SDD)
  • RAID controllers
  • Data transfer and storage systems

Deliverables

Source code (source code license only)

  • VHDL Source Code

VHDL verification environment

  • Tests with reference responses

Technical documentation

  • Datasheet
  • Installation notes
  • User manual

Instantiation templates

Example design

Technical support

  • IP Core implementation support

Variable length maintenance

  • Delivery of IP Core updates, minor and major changes
  • Delivery of documentation updates
  • Telephone & email support
  • Licensing

    Netlist License

    • Post-synthesis netlist
    • Implementation scripts
    • Constraints
    • Instantiation template
    • Documentation

    VHDL Source License

    • VHDL RTL source code
    • Complete verification plan together with testbenches needed to verify correct operation of the core
    • Vectors for testing the functionality of the core
    • Simulation & implementation scripts
    • Documentation

    Documentation

    Datasheet

    For more information about the So-Logic SATA-III Host Controller core, please see the following datasheet:

    Reference Design and Evaluation Version

    Reference design as well as evaluation netlist are available for the SATA-III Host Controller core upon the request.

    Reference design comes in a form of bit file for Zynq-7000, Artix-7, Kintex-7, Virtax-7, Virtex-6 and Virtex 5 Xilinx FPGA Evaluation Platforms. Using this reference design, customer can connect it's HDD/SSD to the SATA-III Host Controller core and evaluate the functionality and performance of the core.

    Evaluation netlists are also available upon a request. Using evaluation netlist user can integrate SATA-III Host Controller core into its specific application-related design and evaluate SATA-III Host Controller core performance in the target application for a limited period of time.

    For more information about the reference design, please contact So-Logic at ip_sata2_hctrl@so-logic.net.

    Pricing and Additional Information

    Pricing of SATA-III Host Controller core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the SATA-III Host Controller core, please contact So-Logic at:

    Phone: +43-1-315 77 77-11
    Fax: +43-1-315 77 77-44
    email: ip_sata2_hctrl@so-logic.net

     

    Updated at: 2016-08-19 10:09to the top