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• so-logic
  • Coordinates
    • so-logic Brasil2014-12-04 11:51:36 +0100
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    • Distribution2022-07-08 11:01:29 +0200
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• sozius
  • Kits, Applications, Use Cases2019-07-31 08:09:49 +0200
  • Ethernet2019-07-31 08:05:50 +0200
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• Activities
  • Development2009-11-23 14:43:47 +0100
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  • Network2009-11-23 15:43:20 +0100
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• Knowledgebase
  • FPGA Universe
    • Tutorials
      • Basic FPGA Tutorial - Vivado VHDL v2024.12015-12-18 19:35:36 +0100
      • Basic FPGA Tutorial - Vivado Verilog v2024.12015-12-18 19:35:50 +0100
      • Basic FPGA Tutorial - ISE v14.7, VHDL2015-12-18 19:36:15 +0100
      • Basic Embedded System Design Tutorial v2024.12015-12-18 19:36:27 +0100
      • Basic HLS Tutorial v2024.12016-10-18 16:09:36 +0200
      • Basic SystemC Tutorial v2021.12020-07-05 19:00:06 +0200
      • Basic Functional Verification Tutorial v2024.12021-11-02 11:53:58 +0100
      • VHDL Style Guide2011-01-31 09:56:57 +0100
  • Links
    • Electronic2009-11-26 13:38:44 +0100
    • FPGA2009-11-26 13:47:11 +0100
    • Useful2009-11-26 14:03:01 +0100
  • Quick Reference Guides2009-11-26 14:09:51 +0100
  • Newsletters
    • Newsletter - September 20162016-09-16 10:39:32 +0200
    • Newsletter - February 20162016-01-15 11:59:48 +0100
    • Newsletter - November 20152015-10-29 15:32:44 +0100
    • Newsletter - May 20152015-04-21 11:06:02 +0200
    • Newsletter - March 20152015-04-21 11:02:26 +0200
• Trainings
  • AMD Xilinx
    • AI
      • Designing with Versal AI Engine 1: Architecture and Design Flow2024-10-31 18:42:30 +0100
      • Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels2024-10-31 18:52:49 +0100
      • Designing with Versal AI Engine 3: Kernel Programming and Optimization2024-10-31 19:06:02 +0100
      • Developing AI Inference Solutions with the Vitis AI Platform2024-11-02 19:23:20 +0100
    • Architecture
      • Versal
        • Designing with the Versal Adaptive SoC: Architecture2024-10-31 15:41:04 +0100
        • Designing with the Versal Adaptive SoC: Design Methodology2024-10-31 15:49:17 +0100
        • Designing with the Versal Adaptive SoC: Power and Board Design2024-10-31 16:45:41 +0100
        • Designing with the Versal Adaptive SoC: Memory Interfaces2024-10-31 16:01:34 +0100
        • Designing with the Versal Adaptive SoC: Hardware Debug2024-10-31 15:55:26 +0100
      • Designing with the UltraScale and UltraScale+ Architectures2024-10-31 15:30:21 +0100
      • Designing with AMD Xilinx 7 Series Families2016-08-03 09:43:39 +0200
      • Legacy
        • Designing with Spartan-6 and Virtex-6 Families2012-01-18 17:23:35 +0100
        • Spartan-6 with ISE Migration to 7 Series with Vivado2022-08-15 12:06:01 +0200
        • Designing with Virtex-5 FPGA Family2023-03-16 15:16:52 +0100
        • Designing with Virtex-4 Family2012-01-18 17:41:29 +0100
      • Versal Live Online Workshop Compendium Complete
        • AMD Versal Compendium 1 : Architecture2023-03-17 10:22:26 +0100
        • AMD Versal Compendium 2 : High Speed Communication2021-08-18 22:47:40 +0200
        • AMD Versal Compendium 3 : AI Engine2021-09-08 10:44:21 +0200
    • Connectivity
      • Designing with the Versal Adaptive SoC: Serial Transceivers2024-10-31 16:54:44 +0100
      • Designing with the Versal Adaptive SoC: PCI Express Systems2024-10-31 16:12:47 +0100
      • Designing with the Versal Adaptive SoC: Network on Chip2024-10-31 16:06:25 +0100
      • Designing with the Zynq UltraScale+ RFSoC2024-11-01 11:54:32 +0100
      • How to Design a High-Speed Memory Interface2023-03-16 15:21:10 +0100
      • PCIe Protocol Overview2019-07-24 09:15:44 +0200
      • Designing an Integrated PCI Express System2023-03-16 15:22:53 +0100
      • Designing with Multi-Gigabit Serial I/O2023-03-16 15:23:47 +0100
      • Designing with Ethernet MAC Controllers2023-03-16 15:24:54 +0100
      • Signal Integrity and Board Design for AMD Xilinx FPGAs2023-03-16 11:24:46 +0100
      • Designing with AMD Xilinx Serial Transceivers2023-03-16 11:26:07 +0100
    • DSP
      • High-Level Synthesis with Vitis HLS2024-11-02 20:53:05 +0100
      • Vitis Model Composer: A MATLAB and Simulink-based Product2024-11-03 14:42:09 +0100
      • C++ for Adaptive SOC2023-05-20 09:08:01 +0200
      • Essential DSP Implementation Techniques for Xilinx FPGAs2023-03-16 15:28:00 +0100
      • Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework2024-11-02 19:37:12 +0100
    • Embedded
      • Adaptive SoCs for System Architects2024-10-31 12:32:45 +0100
      • Embedded Heterogeneous Design2024-11-02 20:41:59 +0100
      • Operating Systems and Hypervisors in Adaptive SoCs2024-11-03 14:26:32 +0100
      • Zynq UltraScale+ MPSoC: Boot and Platform Management2024-11-03 14:49:56 +0100
      • Zynq UltraScale+ MPSoC for the Hardware Designer 2024-11-03 14:46:00 +0100
      • Zynq All Programmable SoC System Architecture2016-08-03 11:42:51 +0200
      • Migrating to the Vitis Unified IDE2024-11-03 12:32:24 +0100
      • Embedded Design with PetaLinux Tools2024-11-02 19:47:36 +0100
      • Embedded Systems Design2024-11-02 20:46:07 +0100
      • Embedded Systems Software Design2024-11-02 19:54:33 +0100
      • Accelerating Applications with the Vitis Unified Software Environment2024-10-31 12:34:49 +0100
    • Languages
      • Designing with VHDL2024-11-02 19:17:35 +0100
      • Advanced VHDL2024-03-05 18:19:26 +0100
      • Designing with Verilog2024-11-03 15:29:13 +0100
      • Designing with System Verilog2024-03-07 10:31:40 +0100
      • Verification with System Verilog2024-03-07 10:30:44 +0100
    • Tools
      • Designing with the IP Integrator Tool2024-10-31 15:19:56 +0100
      • Vitis Design flow2023-03-17 10:12:58 +0100
      • Designing FPGAs Using the Vivado Design Suite 12024-10-31 14:37:16 +0100
      • Designing FPGAs Using the Vivado Design Suite 22024-10-31 14:47:02 +0100
      • Designing FPGAs Using the Vivado Design Suite 32024-10-31 15:07:27 +0100
      • Designing FPGAs Using the Vivado Design Suite 42024-10-31 15:12:59 +0100
      • UltraFast Design Methodology2024-11-03 14:32:09 +0100
      • Design Closure Techniques2024-11-03 15:33:03 +0100
      • DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite2024-11-02 19:40:05 +0100
  • Doulos
  • Mathworks
    • MATLAB Grundlagen2019-07-22 16:03:12 +0200
    • Machine Learning mit MATLAB2017-06-27 11:02:03 +0200
    • MATLAB Programmiertechniken2015-10-28 12:07:25 +0100
    • Programmierung von AMD Xilinx Zynq SoCs mit MATLAB und Simulink2015-10-28 12:08:43 +0100
    • Simulink zur System- und Algorithmenmodellierung2015-10-28 12:10:10 +0100
    • Signalverarbeitung mit Simulink2015-10-28 12:09:39 +0100
    • Objektorientierte Programmierung mit MATLAB2017-06-27 11:01:59 +0200
  • National Instruments
  • so-logic
    • Design Compendium Yocto for AMD Xilinx devices2024-03-07 14:39:05 +0100
    • Design Compendium Embedded System for AMD Xilinx devices2024-03-07 14:30:34 +0100
    • Design Compendium Verification for AMD Xilinx devices2024-03-07 14:32:55 +0100
    • Design Compendium VHDL for AMD Xilinx devices2024-03-07 12:14:55 +0100
    • Design Compendium System Verilog for AMD Xilinx devices2024-03-07 12:19:24 +0100
    • Design Compendium High Level Synthesis for AMD Xilinx devices2024-03-07 12:27:32 +0100
    • Design Compendium High Level SystemC for AMD Xilinx devices2024-03-07 12:21:09 +0100
    • High Level Synthesis
      • C++2011-12-27 08:02:25 +0100
      • SystemC TLM2011-12-27 10:13:09 +0100
      • SystemC Concepts2011-12-27 16:00:25 +0100
  • Payment conditions2020-10-17 09:26:17 +0200
  • Instruction2012-01-10 09:24:24 +0100
• IP Cores
  • Interface Cores
    • Ethernet
      • 10/100/1000 Mb/s Ethernet
        • 10/100/1000 Mb/s MAC Controller Core2019-05-08 12:50:02 +0200
        • 1000BASE-X PCS Core2019-05-08 13:38:39 +0200
        • 10/100/1000 Mb/s MAC Configurator Core2019-05-09 12:12:08 +0200
        • Ethernet GMII Core2019-05-09 12:20:11 +0200
        • Ethernet GMII2MII Core2019-05-09 12:55:21 +0200
        • Ethernet GMII2RGMII Core2019-05-10 15:33:42 +0200
      • 10G Ethernet
        • 10G MAC Controller Core2019-05-08 13:50:25 +0200
        • 10GBASE-R PCS Core2019-05-08 13:56:03 +0200
        • 10 Gb/s Ethernet MAC Configurator Core2019-05-10 15:48:27 +0200
      • Utility Ethernet Cores
        • Ethernet Pause Generator Core2019-05-09 17:06:47 +0200
        • Generator Checker Core2019-05-10 15:53:30 +0200
      • Encryption Ethernet Cores
        • AES Core2019-05-24 17:26:59 +0200
      • Miscellaneous Ethernet Cores
        • ARP Decoder Core2019-05-24 12:19:09 +0200
        • ARP Encoder Core2019-05-24 12:19:25 +0200
        • ARP Packet Core2019-05-24 12:19:48 +0200
        • ARP Table Core2019-05-24 12:20:14 +0200
        • Capture Register Core2019-05-24 12:20:41 +0200
        • Error Statistics Core2019-05-24 12:21:00 +0200
        • Ethernet Encoder Core2019-05-21 11:29:47 +0200
        • Ethernet Decoder Core2019-05-20 17:15:48 +0200
        • ICMP Decoder Core2019-05-24 12:22:06 +0200
        • ICMP Encoder Core2019-05-24 12:22:32 +0200
        • IP Decoder Core2019-05-24 12:22:52 +0200
        • IP Encoder Core2019-05-24 12:23:13 +0200
        • Ethertype2dest Core2019-05-24 12:23:31 +0200
        • Network Packet FIFO Core2019-05-24 12:24:08 +0200
        • Port2tdest Core2019-05-24 12:24:31 +0200
        • Protocol2tdest Core2019-05-24 12:24:55 +0200
        • Tdest2ethertype Core2019-05-24 12:26:31 +0200
        • Tdest2port Core2019-05-24 12:26:49 +0200
        • Protocol2protocol Core2019-05-24 12:27:07 +0200
        • Time Stamp Counter Core2019-05-24 12:27:29 +0200
        • UDP Decoder Core2019-05-24 12:27:55 +0200
        • UDP Encoder Core2019-05-24 12:28:15 +0200
        • UDP Register Handler Core2019-05-24 12:28:34 +0200
    • Serial ATA
      • SATA-II Host Controller Core2016-08-19 10:11:50 +0200
      • SATA-III Host Controller Core2016-08-19 10:09:48 +0200
  • Machine Learning Cores
    • Ensemble Classifiers Cores
      • Ensemble Inference Cores
        • Decision Tree Ensemble Inference Core2011-01-15 22:22:15 +0100
      • Ensemble Evaluation Cores
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Pipelined Architecture2010-11-20 14:50:36 +0100
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Pipelined Architecture2010-11-20 14:51:18 +0100
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Serial Architecture2010-11-20 14:54:00 +0100
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Serial Architecture2010-11-20 14:55:23 +0100
      • Combination Rules Cores
        • Behavior Knowledge Space Core - Parallel Architecture2010-11-20 14:56:13 +0100
        • Behavior Knowledge Space Core - Serial Architecture2010-11-20 14:56:40 +0100
        • Weighted Majority Voting Core - Parallel Architecture2010-11-20 14:57:16 +0100
        • Majority Voting Core - Parallel Architecture2010-11-20 14:57:51 +0100
        • Majority Voting Core - Serial Architecture2010-11-20 14:58:16 +0100
    • Decision Trees Cores
      • Decision Tree Inference Core2010-11-20 14:58:43 +0100
      • Decision Tree Core using Serial Architecture2010-11-20 14:59:20 +0100
      • Decision Tree Core using Pipelined Architecture2010-11-20 14:59:53 +0100
  • Processor and Microcontroller Cores
    • 8051 Microcontroller Cores2011-01-16 09:52:01 +0100
  • Finished and IP Cores Under Development2016-08-18 17:11:11 +0200
• Customers