Site map

• so-logic
  • Coordinates
    • so-logic Brasil2014-12-04 11:51:36 +0100
    • so-logic Serbia2015-01-23 15:11:46 +0100
  • History2021-02-07 19:24:42 +0100
  • Networking
    • Distribution2019-07-18 10:59:46 +0200
    • Education2019-10-31 11:35:44 +0100
    • Development2019-07-22 12:12:26 +0200
    • Cooperations2019-07-22 14:53:23 +0200
  • Staff2021-05-05 17:34:46 +0200
  • After work
    • Hotels2019-07-11 09:28:01 +0200
    • Restaurants2019-07-23 09:52:58 +0200
    • Bars & Cafés2019-07-11 10:56:21 +0200
    • Culture2019-07-11 09:19:41 +0200
  • Gallery
    • Boards2009-11-20 08:39:22 +0100
    • Beargallery2009-11-20 08:46:51 +0100
  • Privacy and Policy2019-07-22 15:33:25 +0200
• sozius
  • Kits, Applications, Use Cases2019-07-31 08:09:49 +0200
  • Ethernet2019-07-31 08:05:50 +0200
  • JTAG2019-07-31 08:01:14 +0200
  • PMOD2019-07-31 07:59:42 +0200
  • Audio2019-07-31 07:58:23 +0200
  • MCAM2019-07-31 12:43:42 +0200
• Activities
  • Development2009-11-23 14:43:47 +0100
  • Coaching - Consulting2009-11-23 14:53:41 +0100
  • Reviews2009-11-23 15:08:07 +0100
  • Feasibility studies2009-11-23 15:12:51 +0100
  • Prototyping2014-05-26 14:58:36 +0200
  • Network2009-11-23 15:43:20 +0100
  • Hosting2009-11-23 15:50:48 +0100
  • Webservice2009-11-23 15:55:03 +0100
• Knowledgebase
  • FPGA Universe
    • Tutorials
      • Basic FPGA Tutorial - Vivado VHDL v2020.12015-12-18 19:35:36 +0100
      • Basic FPGA Tutorial - Vivado Verilog v2020.12015-12-18 19:35:50 +0100
      • Basic FPGA Tutorial - ISE v14.7, VHDL2015-12-18 19:36:15 +0100
      • Basic Embedded System Design Tutorial v2020.12015-12-18 19:36:27 +0100
      • Basic HLS Tutorial v2020.12016-10-18 16:09:36 +0200
      • Basic SystemC Tutorial v2020.12020-07-05 19:00:06 +0200
      • VHDL Style Guide2011-01-31 09:56:57 +0100
  • Links
    • Electronic2009-11-26 13:38:44 +0100
    • FPGA2009-11-26 13:47:11 +0100
    • Useful2009-11-26 14:03:01 +0100
  • Quick Reference Guides2009-11-26 14:09:51 +0100
  • Newsletters
    • Newsletter - September 20162016-09-16 10:39:32 +0200
    • Newsletter - February 20162016-01-15 11:59:48 +0100
    • Newsletter - November 20152015-10-29 15:32:44 +0100
    • Newsletter - May 20152015-04-21 11:06:02 +0200
    • Newsletter - March 20152015-04-21 11:02:26 +0200
• Trainings
  • soopendays 20122019-07-31 08:16:18 +0200
  • Doulos
    • Xilinx - Vivado FPGA Essentials (Online)2016-01-15 11:57:40 +0100
    • Xilinx - Vivado Adopter Class (Live Online)2016-01-15 12:03:09 +0100
    • Essential Tcl for Vivado (Online) 2016-01-15 12:09:47 +0100
    • Xilinx - Vivado HLS (Online)2016-01-15 12:14:34 +0100
    • Xilinx - Designing with the UltraScale Architecture (Online)2016-01-15 11:52:19 +0100
  • Mathworks
    • MATLAB Grundlagen2019-07-22 16:03:12 +0200
    • Machine Learning mit MATLAB2017-06-27 11:02:03 +0200
    • MATLAB Programmiertechniken2015-10-28 12:07:25 +0100
    • Programmierung von Xilinx Zynq SoCs mit MATLAB und Simulink2015-10-28 12:08:43 +0100
    • Simulink zur System- und Algorithmenmodellierung2015-10-28 12:10:10 +0100
    • Signalverarbeitung mit Simulink2015-10-28 12:09:39 +0100
    • Objektorientierte Programmierung mit MATLAB2017-06-27 11:01:59 +0200
  • National Instruments
    • Labview Basic I2012-01-18 16:35:58 +0100
    • Compact RIO + FPGA2012-01-18 16:36:35 +0100
  • so-logic
    • Art of FPGA Design
      • Principles of FPGA Design2011-12-26 09:16:15 +0100
      • Use Cases for FPGAs2011-12-26 09:41:24 +0100
      • High Speed Serial IOs with FPGA2009-12-04 11:20:11 +0100
      • Embedded System Ideas and Concepts2018-01-26 14:36:23 +0100
      • Implementation of a digital Receiver with FPGAs2009-12-04 11:40:59 +0100
      • High Speed DSP Design with FPGAs2018-01-26 14:38:11 +0100
      • Embedded System Design with FPGAs2009-12-04 11:14:30 +0100
    • High Level Synthesis
      • C++2011-12-27 08:02:25 +0100
      • SystemC TLM2011-12-27 10:13:09 +0100
      • SystemC Concepts2011-12-27 16:00:25 +0100
  • Xilinx
    • Architecture
      • Designing with Versal AI Engine 1 - Architecture and Design Flow2021-07-18 16:14:33 +0200
      • Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels2021-07-18 16:35:11 +0200
      • Designing with Versal AI Engine 3: Kernel Programming and Optimization2021-07-18 17:11:54 +0200
      • Designing with the Versal ACAP: PCI Express Systems2021-07-18 15:59:33 +0200
      • Designing with the Versal ACAP: Network on Chip2021-07-11 21:59:33 +0200
      • Designing with the Versal ACAP: Architecture and Methodology2021-07-11 21:27:54 +0200
      • Getting Started with the Xilinx Versal ACAP Platform2021-07-06 23:06:24 +0200
      • Designing with the Zynq UltraScale+ RFSoC2019-07-23 12:17:36 +0200
      • Zynq SoC System Architecture2019-07-23 12:41:09 +0200
      • Designing with the UltraScale and UltraScale+ Architectures2019-07-23 14:14:53 +0200
      • Designing with Xilinx 7 Series Families2016-08-03 09:43:39 +0200
      • Designing with Spartan-6 and Virtex-6 Families2012-01-18 17:23:35 +0100
      • Designing with Virtex-5 FPGA Family2012-09-10 10:16:01 +0200
    • Connectivity
      • How to Design a High-Speed Memory Interface2019-07-24 08:48:26 +0200
      • PCIe Protocol Overview2019-07-24 09:15:44 +0200
      • Designing an Integrated PCI Express System2019-07-24 09:21:17 +0200
      • Designing with Multi-Gigabit Serial I/O2019-07-24 09:27:40 +0200
      • Designing with Ethernet MAC Controllers2019-07-24 09:30:28 +0200
      • Signal Integrity and Board Design for Xilinx FPGAs2013-07-01 13:11:35 +0200
      • Designing with Xilinx Serial Transceivers2019-07-08 10:58:42 +0200
      • Designing with UltraScale FPGA Transceivers2016-08-03 10:56:01 +0200
    • DSP
      • Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment2019-11-04 16:17:25 +0100
      • Essential DSP Implementation Techniques for Xilinx FPGAs2018-11-11 14:10:06 +0100
      • DSP Design Using System Generator2018-11-11 13:59:02 +0100
      • C-based Design: High-Level Synthesis with Vivado HLS2016-08-03 11:29:25 +0200
      • C-based HLS Coding for Software Designers2012-09-28 12:16:03 +0200
      • C-based HLS Coding for Hardware Designers2012-09-28 12:16:36 +0200
    • Embedded
      • Advanced SDSoC Development Environment and Methodology2018-06-13 11:45:32 +0200
      • Developing AWS F1 Applications Using the SDAccel Environment2019-07-24 10:08:29 +0200
      • Zynq All Programmable SoC System Architecture
        • Zynq All Programmable SoC System Architecture2019-11-04 15:00:13 +0100
      • Embedded Open-Source Linux Development2018-11-11 14:00:22 +0100
      • Embedded Design with PetaLinux Tools2016-08-03 11:50:41 +0200
      • Embedded Systems Design2018-11-11 14:02:14 +0100
      • Advanced Features and Techniques of Embedded Systems Design2016-08-03 12:26:46 +0200
      • Embedded Systems Software Design2018-11-11 14:02:45 +0100
      • Advanced Features and Techniques of Embedded Systems Software Design 2018-11-11 14:03:19 +0100
      • Embedded C/C++ SDSoC Development Environment and Methodology2018-11-11 14:01:04 +0100
      • Zynq UltraScale+ MPSoC for the Hardware Designer 2018-11-11 14:05:23 +0100
      • Zynq UltraScale+ MPSoC for the Software Developer2018-11-11 14:05:49 +0100
      • Zynq UltraScale+ MPSoC for the System Architect 2019-07-24 10:23:12 +0200
      • Developing and Optimizing Applications Using the OpenCL Framework for FPGAs2017-03-22 13:10:17 +0100
    • Languages
      • Designing with VHDL2018-11-11 14:09:40 +0100
      • Advanced VHDL2019-07-24 10:40:29 +0200
      • Designing with Verilog2018-11-18 10:36:23 +0100
      • Designing with System Verilog2018-11-11 14:08:13 +0100
      • Verification with System Verilog2018-11-11 14:11:25 +0100
    • Tools
      • Vivado Design Suite for ISE Project Navigator Users2019-07-24 11:54:43 +0200
      • Designing FPGAs Using the Vivado Design Suite 12018-11-18 10:45:12 +0100
      • Designing FPGAs Using the Vivado Design Suite 22018-11-18 10:46:11 +0100
      • Designing FPGAs Using the Vivado Design Suite 32018-11-18 10:46:38 +0100
      • Designing FPGAs Using the Vivado Design Suite 42019-07-24 12:10:11 +0200
      • UltraFast Design Methodology2018-11-18 10:44:20 +0100
      • Vivad Design Suite for ISE Software Project Navigator Users2013-07-02 13:40:47 +0200
      • Vivado Advanced XDC and Static Timing Analysis for ISE Software Users2018-11-18 10:48:50 +0100
      • Partial Reconfiguration Tools & Techniques2018-11-18 10:43:02 +0100
    • Designing FPGAs with Xilinx Vivado Tools 2019-12-08 20:08:08 +0100
    • Yocto Advanced2020-07-21 14:05:44 +0200
    • Yocto Basic2020-02-26 16:33:28 +0100
    • RFSoc and Yocto for FPGA2020-10-17 09:38:39 +0200
  • Payment conditions2020-10-17 09:26:17 +0200
  • Instruction2012-01-10 09:24:24 +0100
• IP Cores
  • Interface Cores
    • Ethernet
      • 10/100/1000 Mb/s Ethernet
        • 10/100/1000 Mb/s MAC Controller Core2019-05-08 12:50:02 +0200
        • 1000BASE-X PCS Core2019-05-08 13:38:39 +0200
        • 10/100/1000 Mb/s MAC Configurator Core2019-05-09 12:12:08 +0200
        • Ethernet GMII Core2019-05-09 12:20:11 +0200
        • Ethernet GMII2MII Core2019-05-09 12:55:21 +0200
        • Ethernet GMII2RGMII Core2019-05-10 15:33:42 +0200
      • 10G Ethernet
        • 10G MAC Controller Core2019-05-08 13:50:25 +0200
        • 10GBASE-R PCS Core2019-05-08 13:56:03 +0200
        • 10 Gb/s Ethernet MAC Configurator Core2019-05-10 15:48:27 +0200
      • Utility Ethernet Cores
        • Ethernet Pause Generator Core2019-05-09 17:06:47 +0200
        • Generator Checker Core2019-05-10 15:53:30 +0200
      • Encryption Ethernet Cores
        • AES Core2019-05-24 17:26:59 +0200
      • Miscellaneous Ethernet Cores
        • ARP Decoder Core2019-05-24 12:19:09 +0200
        • ARP Encoder Core2019-05-24 12:19:25 +0200
        • ARP Packet Core2019-05-24 12:19:48 +0200
        • ARP Table Core2019-05-24 12:20:14 +0200
        • Capture Register Core2019-05-24 12:20:41 +0200
        • Error Statistics Core2019-05-24 12:21:00 +0200
        • Ethernet Encoder Core2019-05-21 11:29:47 +0200
        • Ethernet Decoder Core2019-05-20 17:15:48 +0200
        • ICMP Decoder Core2019-05-24 12:22:06 +0200
        • ICMP Encoder Core2019-05-24 12:22:32 +0200
        • IP Decoder Core2019-05-24 12:22:52 +0200
        • IP Encoder Core2019-05-24 12:23:13 +0200
        • Ethertype2dest Core2019-05-24 12:23:31 +0200
        • Network Packet FIFO Core2019-05-24 12:24:08 +0200
        • Port2tdest Core2019-05-24 12:24:31 +0200
        • Protocol2tdest Core2019-05-24 12:24:55 +0200
        • Tdest2ethertype Core2019-05-24 12:26:31 +0200
        • Tdest2port Core2019-05-24 12:26:49 +0200
        • Protocol2protocol Core2019-05-24 12:27:07 +0200
        • Time Stamp Counter Core2019-05-24 12:27:29 +0200
        • UDP Decoder Core2019-05-24 12:27:55 +0200
        • UDP Encoder Core2019-05-24 12:28:15 +0200
        • UDP Register Handler Core2019-05-24 12:28:34 +0200
    • Serial ATA
      • SATA-II Host Controller Core2016-08-19 10:11:50 +0200
      • SATA-III Host Controller Core2016-08-19 10:09:48 +0200
  • Machine Learning Cores
    • Ensemble Classifiers Cores
      • Ensemble Inference Cores
        • Decision Tree Ensemble Inference Core2011-01-15 22:22:15 +0100
      • Ensemble Evaluation Cores
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Pipelined Architecture2010-11-20 14:50:36 +0100
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Pipelined Architecture2010-11-20 14:51:18 +0100
        • Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Serial Architecture2010-11-20 14:54:00 +0100
        • Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Serial Architecture2010-11-20 14:55:23 +0100
      • Combination Rules Cores
        • Behavior Knowledge Space Core - Parallel Architecture2010-11-20 14:56:13 +0100
        • Behavior Knowledge Space Core - Serial Architecture2010-11-20 14:56:40 +0100
        • Weighted Majority Voting Core - Parallel Architecture2010-11-20 14:57:16 +0100
        • Majority Voting Core - Parallel Architecture2010-11-20 14:57:51 +0100
        • Majority Voting Core - Serial Architecture2010-11-20 14:58:16 +0100
    • Decision Trees Cores
      • Decision Tree Inference Core2010-11-20 14:58:43 +0100
      • Decision Tree Core using Serial Architecture2010-11-20 14:59:20 +0100
      • Decision Tree Core using Pipelined Architecture2010-11-20 14:59:53 +0100
  • Processor and Microcontroller Cores
    • 8051 Microcontroller Cores2011-01-16 09:52:01 +0100
  • Finished and IP Cores Under Development2016-08-18 17:11:11 +0200
• Customers