Staff

Name	Email*	GSM number	Extension**	Activity
Peter Thorwartl	thor	+43-664-41 60 188	81	Geschäftsführer, Trainer und System Designer
Daniela Thorwartl	dth1	+43-664-10 53 069	11	Sekretariat, Training und Organisation
Alfred Bruckner	abr1	+43-664-822 61 77	-	System Designer, Circuit Designer und Layouter
Martin Küng	mku1	+43-660-6419901	-	3D Design und Druck
Heinrich Thurner	h.thurner	-	-	System Administrator
Andreas Frühwirth	fr1	+43-664-84 70 988	28	Logic designer and high speed serial IO specialist
Christian Buchinger	cbu1	-	20	-
Thiago Carneiro	thc1	-	46	-
Maja Gordic	mgo1	-	11	Embedded System Design using FPGAs
Bernhard Greissing	bgr1	+43-664-82 04 135	30	System Designer, Circuit Designer und Layouter
Markus Kreuzinger	mkr1	+43-699-190 269 01	84	VHDL Developer
Lukas Lichtl	lli1	-	22	-
Leopold Matzinger	lma1	+43-664-82 10 577	22	Embedded Software Developer und embedded System Designer
Franz Wittmann	fwi1	-	27	-
Paul Wolfger	pwo1	-	86	-
Samed Asil	saa1	-	-	Test and commissioning

* Hinzufügen zu @so-logic.net
** Rufe +43-1-315 77 77 plus Durchwahl

Geschäftsführer Peter Thorwartl

Geboren: 1968 in Wien
Kolleg in Nachrichtentechnik
1996: Abschluss des Studiums Elektrotechnik an der Technischen Universität Wien (Professoren Paschke, Pötzl, Prechtl, Hoffmann, Mecklenbräuker)
Während meines Studiums war ich oft Unterrichtsassistent
Von 1991 bis 1997 unterrichtete ich am Kolleg für Kommunikationstechnik in Wien
1997: Zivildienst im AKH (Allgemeines Krankenhaus, eines der größten Krankenhäuser der Welt)
1996-2000: Vortragender und Trainier über FPGA-Design an der Technischen Universität Wien
1997: Gründung von So-logic GmbH & Co KEG
Seit 2000 Xilinx-Training-Center für FPGA-Design
2003 - 2004: Vortragender und Trainier über FPGA und Computer-Architecture an der Fachhochschule (FH Wien)
Seit 2008: Vortragender über Embedded Systems an der FH Wiener Neustadt.

Meine Erfahrung sammelte ich in einer der führenden Universiäten von Zentral- und Osteuropa. Neben meiner wissenschaftlichen Arbeiten war ich auch Vortragender an Universitäten und HTLs.

Daniela Thorwartl

	I was born in Brasil and speak following languages: Portuguese, Italian, English, Spanish, German.

Alfred Bruckner

1964 born in Vienna
1983 successfully graduated College HTL Schellinggasse (1010 Wien) (Communications Engeneering)
1984 Alcatel (former ITT) Austria
- Testing and engineering prototype hardware
- Assembler an C-language coded Operating system and Debug Software
- Adoption, development and certification of a digital Telephony system for various countries
- Hardware development of a complete range of small to large voicemail systems for digital telephony systems which are DSP and X86 based and run a proprietary and linux operating system
2000 Tecwings
- Hardware development of a Multimedia Settop box for MPEG4 video
- Various developments according to customer specification
- DC/DC power supply developments
2004 so-logic
- FPGA and PowerPC based redundant hardware design
- 300A FET based starter relay
- Ultra compact platform for GSM/GPS tracking
- 200W DC/DC switching power supply and battery charging
- High speed FPGA Video transmission

Skills:

Experience in various Intel Processor platforms (8051, 80x86, Pentium, DSPs), PowerPC, PIC, ATMEL
Assembly and C-language
Discrete analog circuit design and Spice based analog simulation
DC/DC switching applications
Digital high speed circuit designs and FPGA design
Circuit design entry, PCB layout (HDI, Starrflex)
Hardware design simulation, validation and verification
Systems design, EMC conform development

Andreas Frühwirth

1975 born in Krems
1992 graduation at BFS "aeronautics" in Langenlebarn
1997 graduation at HTL "communications engineering" in Vienna
1997 Philips Tone testing of fax machines Development of automated test systems
1999 Neuroth / Analog Devices Inc.Test hardware development and measurement for HDSL chips, ASIC design and simulation of a G.SHDSL chip
2003 On-demand Microelectronics Test hardware development ASIC design of a vector processing (VSP) chip
2004 SoLogic FPGA design (Xilinx) for various customers (CPU peripherals, SDI SD/HD video, PCIe, etc.ASIC design of the VSP video (SVEN) chip)

Born in Brazil 1986
Graduated from School of Technology, University of Campinas - UNICAMP - Brazil - 2009
I'm learning German at VWU for my master degree in Software Engineering at TU.

Undergradute Projects
Network Technologies Publication, Yr II No I 2008. "Frequency Control of Piezoelectric Transducers Operation Using Programmable Logic Devices".
ANDESCON 2008 paper presentation in Cusco, Peru: "A Driver for Piezoelectric Transducers with Automatic Resonance Correction".
International Congress on Ultrasonic's - 2009 at University of Santiago, Chile: "An electronic amplifier for piezoelectric transducers"

Work Experience
Trainee in the Department of Network Management Systems (GRSD) School of Electrical and Computer Engineering (FEEC), UNICAMP Campinas-SP Brazil.

Maja Gordic

I was born in Novi Sad in 1981.

In 2008 I have graduated from the Faculty of Technical Sciences in Novi Sad, at the department of Microprocessor Electronics. My Master thesis was in the area of embedded system design using FPGAs.

My hobbies are sports and reading.

Bernhard Greissing

1989 I started studying Electrical Engineering / Computer Technology at the Vienna University of Technology
1996 together with a friend we established our own company for professional audio and broadcast engineering
2003 the company changed it's focus so I left with all the engineering equipment which since
2004 is housed at so-Logic

Currently I'm concentrating on circuit design and PCB layout of complex FPGA based systems

Areas of my expertise:

High-Speed Design / Signal Integrity, EMC
FPGA, CPLD Design
Multilayer, rigid-flex, HDI PCBs
CAD library development
Microcontroller / embedded systems
Analog (audio) design
Firmware (Assembler, C)
Mechanical Design (In-House CNC workshop)
Prototyping & rework

My motto:

Engineering is the art of making what you want from things you can get.

Markus Kreuzinger

2004 – 2008 apprenticeship in mechatronics

2007 – 2010 evening classes

2008 – 2009 alternative civilian service

2009 – 2010 automation technician in company LEA

2010 – 2013 Bachelor of Science in Engineering (BSc), Medical Engineering

2013 – 2015 Graduate Engineer (Dipl. -Ing.) Medical Engineering

2015 - started working for the so-logic company

Lukas Lichtl

2004 – 2009 HTBLA Linz Paul-Hahn-Straße (Litec)

2009 – 2010 Rettungssanitäter

2010 – 2013 Bachelor of Science in Engineering, Medizintechnik

2013 – 2015 Diplom-Ingenier für technisch-wissenschaftliche Beruf, Medizintechnik

2015 – Recht und Wirtschaft für TechnikerInnen, JKU Linz

Geboren in Linz, Österreich in April 1990, ware ich bereits schon immer von Elektronik und Software fasziniert. Noch heute bin ich beeindruckt was durch ein perfektes Zusammenspiel dieser beiden Welten erreicht werden kann. Kombiniert in eine Chip (SoC) scheinen die möglichen Anwendungen in der high-tech Industrie grenzenlos. Es könnte keinen besseren Platz also so-logic geben um mein Wissen und meine Passion in diesem Umfeld voranzutreiben.

Lukas auf LinkedIn

Leopold Matzinger

Personal Profile:

Born in Mödling, Austria in 1968.
Secondary School (BRG) in Vienna.
Higher Technical College for Communication Engineering (EQF Level 6).
1988 First FPGA design in Austria with Xilinx FPGA.
Software development projects (Assembler, C, Forth, Turbo Pascal).
1996 Basic military service (Guard Battalion).
2001 So-logic authorized representative.

Projects for So-Logic:

Schiebel (Mine Searching and CamCopter with Microchip PICs)
Arri (Arrimotion Motion Control, Arriflex 435 with Motorola CPUs, Altera NIOS and Altera FPGAs)
Intel/Lantiq/Infineon (Hi-Speed Chiptester FPGA logic analyser, spectrum analyser and signal generator with PowerPCs and Xilinx Virtex 5)
AVL List (Automotive measurement with TI DSPs, PowerPC, MicroBlaze, Cortex-A9, Cortex-R5, Cortex-A53 and Virtex 4, Virtex 5, Spartan 6, Artix, Zynq 7000, Zynq UltraScale+ and Lattice FPGAs)

Training for So-Logic:

Microchip PIC
Xilinx VHDL, Verilog, C, System Generator, HLS
Xilinx DSP, Gigabit-Transceiver, PCIe, Vivado, EDK, Vitis
Xilinx Virtex, Zynq 7000, Zynq UltraScale+

Additional Experience:

Multiple Xilinx FAE, ATP meetings and train the trainer events
2013 Training in Middle East

Born in 1999 in Leoben
2020: HTL Absolvent; Informationstechnologie,Netzwerktechnik

Changjiang Guo – Intern

Personal Data:

Born on December 10, 2008
Nationality: China

Education:

Current: HTL Spengergasse, Department "Fachschule für Informationstechnik" (Technical School for Information Technology)
09/2019 - 07/2023: Sacré Coeur Wien Währing Secondary School
09/2015 - 06/2019: Sacré Coeur Wien Währing Elementary School

Professional Experience:

2017: Student internship (berufspraktische Tage) at battenfeld-cincinnati Austria GmbH

Skills and Competences:

Languages: German/Chinese (bilingual)
English: good school knowledge

IT Skills:

Basic knowledge of server- and client-side scripting languages (PHP)
Installation and operation of current hardware and software for the multimedia sector
Image editing using professional tools and preparation for the internet
Development of a corporate identity and its graphic preparation for print media
Basic knowledge of network engineering and media technology

Hobbies and Interests: