How to Design a High-Speed Memory Interface

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Course Description

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs.

Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.

The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.

Release Date

July 2015

Level

Connectivity 3

Training Duration

2 days

Who Should Attend?

  • FPGA designers and logic designers

Prerequisites

  • VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
  • Familiarity with logic design: state machines and synchronous design
  • Very helpful to have:
    • Basic knowledge of FPGA architecture
    • Familiarity with Xilinx implementation tools
  • Nice to have:
    • Familiarity with I/O basics
    • Familiarity with high-speed I/O standard

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the FPGA resources required for memory interfaces
  • Describe different types of memories
  • Utilize the Xilinx tools to generate memory interface designs
  • Simulate memory interfaces with the Xilinx Vivado simulator
  • Implement memory interfaces
  • Identify the board design options for the realization of memory interfaces
  • Test and debug your memory interface design
  • Run basic memory interface signal integrity simulations

Course Outline

Day 1

  • Course Introduction
  • 7 Series FPGAs Overview
  • Memory Devices
  • 7 Series Memory Interface Resources
  • Memory Controller Details and Signals
  • MIG Design Generation
  • Lab 1: MIG Core Generation
  • MIG Design Simulation
  • Lab 2: MIG Design Simulation

Day 2

  • MIG Design Implementation
  • Lab 3: MIG Design Implementation
  • Memory Interface Test and Debugging
  • Lab 4: MIG Design Debugging
  • MIG in Embedded Designs
  • Lab 5: MIG in IP Integrator
  • Memory Interface Board-Level Design
  • DDR3 PCB Simulation (optional)
  • Lab 6:DDR3 Signal Integrity Simulation (optional)

Lab Descriptions

  • Lab 1: MIG Core Generation – Create a DDR3 memory controller using the Memory Interface Generator (MIG) in the Vivado IP catalog. Customize the soft core memory controller for the board.
  • Lab 2: MIG Design Simulation – Simulate the memory controller created in Lab 1 using the Vivado simulator or Mentor Graphics QuestaSim simulator.
  • Lab 3: MIG Design Implementation – Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.
  • Lab 4: MIG Design Debugging – Debug the memory interface design utilizing the Vivado logic analzyer.
  • Lab 5: MIG in IP Integrator – Use the block design editor to include the MIG IP in a given processor design.
  • Lab 6: DDR3 Signal Integrity Analysis – Learn basic signal analysis options to check waveforms and design optimization (optional).

Event Schedule

so-logic (top1) (Austria)
  • 14.02. - 15.02.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 04.04. - 05.04.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 16.05. - 17.05.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 11.07. - 12.07.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 22.08. - 23.08.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 10.10. - 11.10.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 28.11. - 29.11.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2016-08-03 13:34to the top