Designing with the Zynq UltraScale+ RFSoC

This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...

Course Description

This course provides an overview of the hard block capabilities for the AMD Zynq UltraScale+ RFSoC family, with emphasis on the RF Data Converter and Soft-Decision FEC blocks. It covers configuration, simulation, implementation, hardware verification, power estimation, and PCB considerations for high-speed mixed-signal devices. Gen 1, Gen 2, and Gen 3 devices are included, along with an introduction to the RFSoC DFE IP cores.

The emphasis of this course is on:

• Describing the RFSoC family in general
• Identifying applications for the RF Data Converter and SD-FEC blocks
• Configuring, simulating, and implementing the blocks
• Verifying the RF Data Converter on real hardware
• Reviewing power estimation to identify RFSoC device power demands in various operating modes
• Identifying proper layout and PCB considerations for high-speed analog/digital RFSoC devices
• Covering Gen 1, Gen 2, and Gen 3 devices
• Introducing the RFSoC DFE IP cores

Training Duration

30 hours

Additional Information

• Number of Chapters: 10
• Number of Labs: 16
• Number of Demos: 5
• Current Version: 2025.2

What's New

• All labs and practices have been updated to the latest software versions

Chapters

Chapter 1

• Zynq UltraScale+ RFSoC Overview

Chapter 2

• RF-ADC Hardware

Chapter 3

• RF-DAC Hardware

Chapter 4

• RFSoC Hardware ZCU111

Chapter 5

• Data Converter – Design

Chapter 6

• Data Converter – Practice

Chapter 7

• PCB Design for RFSoC Devices

Chapter 8

• RFSoC Soft-Decision FEC

Chapter 9

• RFSoC DFE

Chapter 10

• Designing with the Zynq UltraScale+ RFSoC Full Course Quiz