Training schedules 2021-07-27 - 2022-07-27

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Event period Training Partner Location Price
02.08. - 02.08.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.08. - 04.08.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.08. - 04.08.2021 09:00-17:00 Designing with the Versal ACAP: PCI Express Systems Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
05.08. - 06.08.2021 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.08. - 06.08.2021 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.08. - 10.08.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.08. - 11.08.2021 09:00-17:00 Zynq All Programmable SoC System Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.08. - 11.08.2021 09:00-17:00 Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels Xilinx so-logic (top1) (Austria) € 1,600.00 Add to cart
11.08. - 12.08.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.08. - 12.08.2021 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.08. - 13.08.2021 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.08. - 13.08.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
13.08. - 13.08.2021 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
16.08. - 18.08.2021 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.08. - 17.08.2021 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.08. - 19.08.2021 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.08. - 20.08.2021 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.08. - 26.08.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.08. - 31.08.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.09. - 01.09.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.09. - 03.09.2021 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.09. - 14.09.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.09. - 17.09.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.09. - 28.09.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.09. - 01.10.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.10. - 04.10.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
04.10. - 06.10.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
05.10. - 06.10.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.10. - 08.10.2021 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.10. - 08.10.2021 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.10. - 13.10.2021 09:00-17:00 Zynq All Programmable SoC System Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.10. - 14.10.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.10. - 14.10.2021 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.10. - 15.10.2021 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.10. - 15.10.2021 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.10. - 15.10.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
18.10. - 19.10.2021 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.10. - 20.10.2021 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.10. - 22.10.2021 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.10. - 22.10.2021 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.10. - 27.10.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.10. - 30.10.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.11. - 03.11.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.11. - 04.11.2021 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
08.11. - 09.11.2021 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.11. - 23.11.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.11. - 26.11.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
29.11. - 30.11.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.11. - 01.12.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.12. - 13.12.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
13.12. - 15.12.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.12. - 16.12.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.12. - 17.12.2021 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.12. - 17.12.2021 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart