Training schedules 2017-02-22 - 2018-02-22

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Event period Training Partner Location Price
24.02. - 24.02.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
24.02. - 24.02.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.02. - 28.02.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.02. - 28.02.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.03. - 03.03.2017 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
01.03. - 02.03.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.03. - 07.03.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.03. - 07.03.2017 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.03. - 09.03.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.03. - 14.03.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.03. - 14.03.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.03. - 16.03.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.03. - 17.03.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.03. - 22.03.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
20.03. - 21.03.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.03. - 23.03.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.03. - 24.03.2017 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.03. - 24.03.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.03. - 29.03.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.03. - 29.03.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
30.03. - 31.03.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.03. - 31.03.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.03. - 31.03.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.04. - 05.04.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.04. - 05.04.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
06.04. - 07.04.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.04. - 07.04.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.04. - 07.04.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.04. - 11.04.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.04. - 13.04.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.04. - 13.04.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.04. - 14.04.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.04. - 14.04.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
18.04. - 19.04.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.04. - 19.04.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.04. - 21.04.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.04. - 25.04.2017 09:00-17:00 MATLAB Grundlagen Mathworks so-logic (top1) (Austria) € 1,200.00 Add to cart
26.04. - 27.04.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.04. - 28.04.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.05. - 02.05.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.05. - 03.05.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.05. - 05.05.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.05. - 05.05.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
08.05. - 10.05.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
08.05. - 09.05.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.05. - 11.05.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.05. - 12.05.2017 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.05. - 12.05.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.05. - 17.05.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.05. - 17.05.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
18.05. - 19.05.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.05. - 19.05.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.05. - 19.05.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.05. - 19.05.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.05. - 19.05.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.05. - 24.05.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
22.05. - 24.05.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
25.05. - 26.05.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.05. - 30.05.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.05. - 01.06.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.05. - 01.06.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.06. - 02.06.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.06. - 02.06.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
05.06. - 06.06.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.06. - 06.06.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.06. - 08.06.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.06. - 13.06.2017 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.06. - 13.06.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.06. - 16.06.2017 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
14.06. - 15.06.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.06. - 20.06.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.06. - 20.06.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.06. - 22.06.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.06. - 23.06.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.06. - 27.06.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.06. - 28.06.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
28.06. - 29.06.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.06. - 30.06.2017 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.06. - 30.06.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
03.07. - 05.07.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.07. - 05.07.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
06.07. - 07.07.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.07. - 07.07.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.07. - 07.07.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.07. - 12.07.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
10.07. - 12.07.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
13.07. - 14.07.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.07. - 14.07.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.07. - 14.07.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.07. - 18.07.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.07. - 20.07.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.07. - 20.07.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.07. - 21.07.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
21.07. - 21.07.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
24.07. - 25.07.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.07. - 27.07.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.07. - 01.08.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.07. - 01.08.2017 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.08. - 04.08.2017 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.08. - 03.08.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.08. - 08.08.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.08. - 08.08.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.08. - 10.08.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.08. - 11.08.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.08. - 15.08.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.08. - 16.08.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,500.00 Add to cart
16.08. - 17.08.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.08. - 18.08.2017 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.08. - 18.08.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
21.08. - 23.08.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.08. - 23.08.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.08. - 23.08.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
24.08. - 25.08.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.08. - 25.08.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.08. - 25.08.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.08. - 30.08.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
31.08. - 01.09.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.08. - 01.09.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.08. - 01.09.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.09. - 05.09.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.09. - 06.09.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.09. - 07.09.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.09. - 08.09.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
08.09. - 08.09.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
11.09. - 12.09.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.09. - 12.09.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.09. - 14.09.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.09. - 19.09.2017 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.09. - 19.09.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.09. - 21.09.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.09. - 22.09.2017 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
25.09. - 26.09.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.09. - 26.09.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.09. - 28.09.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.09. - 29.09.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.10. - 03.10.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.10. - 04.10.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
04.10. - 05.10.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.10. - 06.10.2017 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.10. - 06.10.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
06.10. - 07.10.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.10. - 11.10.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.10. - 11.10.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
12.10. - 13.10.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.10. - 18.10.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.10. - 18.10.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
19.10. - 20.10.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.10. - 20.10.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.10. - 20.10.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 26.10.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 26.10.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.10. - 27.10.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.10. - 27.10.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
30.10. - 31.10.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.10. - 31.10.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.11. - 02.11.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.11. - 03.11.2017 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
06.11. - 07.11.2017 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.11. - 09.11.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.11. - 15.11.2017 09:00-17:00 Simulink zur System- und Algorithmenmodellierung Mathworks so-logic (top1) (Austria) € 1,200.00 Add to cart
16.11. - 17.11.2017 09:00-17:00 MATLAB Programmiertechniken Mathworks so-logic (top1) (Austria) € 1,200.00 Add to cart
20.11. - 21.11.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.11. - 21.11.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.11. - 23.11.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.11. - 24.11.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.11. - 29.11.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
27.11. - 28.11.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.11. - 01.12.2017 09:00-17:00 Embedded Design with PetaLinux Tools Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.12. - 01.12.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
04.12. - 06.12.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.12. - 06.12.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
07.12. - 08.12.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.12. - 08.12.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.12. - 08.12.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.12. - 13.12.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
11.12. - 13.12.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
14.12. - 15.12.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 15.12.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 15.12.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.12. - 19.12.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.12. - 21.12.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.12. - 21.12.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.12. - 22.12.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
22.12. - 22.12.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart