Training schedules 2023-05-29 - 2024-05-29
Event period | Training | Partner | Location | Price | |
---|---|---|---|---|---|
30.05. - 01.06.2023 09:00-17:00 | FPGA Design with Verilog Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
30.05. - 01.06.2023 09:00-17:00 | Embedded Open-Source Linux Development | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
30.05. - 01.06.2023 09:00-17:00 | FPGA Design with VHDL Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
01.06. - 02.06.2023 09:00-17:00 | Embedded Systems Design | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
01.06. - 02.06.2023 09:00-17:00 | Advanced Features and Techniques of Embedded Systems Design | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.06. - 06.06.2023 09:00-17:00 | Designing with Versal AI Engine 1 - Architecture and Design Flow | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.06. - 06.06.2023 09:00-17:00 | Yocto Basic | so-logic | so-logic (top1) (Austria) | € 1,600.00 | |
07.06. - 09.06.2023 09:00-17:00 | Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
07.06. - 07.06.2023 09:00-17:00 | Yocto Advanced | so-logic | so-logic (top1) (Austria) | € 800.00 | |
12.06. - 13.06.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
12.06. - 14.06.2023 09:00-17:00 | Designing with Versal AI Engine 3: Kernel Programming and Optimization | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
14.06. - 15.06.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
14.06. - 15.06.2023 09:00-17:00 | Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
16.06. - 16.06.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
19.06. - 21.06.2023 09:00-17:00 | Designing with Multi-Gigabit Serial I/O | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
19.06. - 19.06.2023 09:00-17:00 | Advanced Features and Techniques of Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
19.06. - 21.06.2023 09:00-17:00 | FPGA Design with SystemC Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
19.06. - 20.06.2023 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
21.06. - 22.06.2023 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
22.06. - 23.06.2023 09:00-17:00 | Designing with UltraScale FPGA Transceivers | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.06. - 27.06.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.06. - 27.06.2023 09:00-17:00 | Vivado Design Suite for ISE Project Navigator Users | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.06. - 26.06.2023 13:00-21:00 | Vitis Design flow | Xilinx | so-logic (top1) (Austria) | € 0.00 | |
28.06. - 29.06.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
30.06. - 30.06.2023 09:00-17:00 | UltraFast Design Methodology | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
30.06. - 30.06.2023 09:00-17:00 | Vivado Design Suite for ISE Software Project Navigator Users | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
25.09. - 25.09.2023 09:00-17:00 | C++ for ASOC | Xilinx | so-logic (top1) (Austria) | € 0.00 | |
27.11. - 27.11.2023 09:00-17:00 | C++ for ASOC | Xilinx | so-logic (top1) (Austria) | € 0.00 | |
15.01. - 15.01.2024 09:00-17:00 | C++ for ASOC | Xilinx | so-logic (top1) (Austria) | € 0.00 |