Training schedules 2017-09-24 - 2018-09-24

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Event period Training Partner Location Price
25.09. - 26.09.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.09. - 27.09.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.09. - 28.09.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.09. - 28.09.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.09. - 28.09.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.10. - 04.10.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
02.10. - 03.10.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.10. - 05.10.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.10. - 06.10.2017 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.10. - 06.10.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
06.10. - 07.10.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.10. - 11.10.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.10. - 11.10.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
10.10. - 11.10.2017 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.10. - 13.10.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.10. - 18.10.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.10. - 18.10.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
17.10. - 18.10.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.10. - 20.10.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.10. - 20.10.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 26.10.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 26.10.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.10. - 27.10.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.10. - 27.10.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
30.10. - 31.10.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.10. - 01.11.2017 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.10. - 01.11.2017 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.11. - 03.11.2017 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
01.11. - 02.11.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.11. - 03.11.2017 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.11. - 07.11.2017 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.11. - 09.11.2017 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.11. - 15.11.2017 09:00-17:00 Simulink zur System- und Algorithmenmodellierung Mathworks so-logic (top1) (Austria) € 1,200.00 Add to cart
16.11. - 17.11.2017 09:00-17:00 MATLAB Programmiertechniken Mathworks so-logic (top1) (Austria) € 1,200.00 Add to cart
20.11. - 21.11.2017 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.11. - 22.11.2017 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
22.11. - 23.11.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.11. - 23.11.2017 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.11. - 29.11.2017 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
27.11. - 28.11.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.11. - 01.12.2017 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.12. - 01.12.2017 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
04.12. - 06.12.2017 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.12. - 06.12.2017 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
05.12. - 06.12.2017 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.12. - 08.12.2017 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.12. - 08.12.2017 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.12. - 08.12.2017 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.12. - 13.12.2017 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
11.12. - 13.12.2017 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
12.12. - 13.12.2017 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 15.12.2017 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 15.12.2017 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.12. - 19.12.2017 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.12. - 21.12.2017 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.12. - 21.12.2017 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.12. - 22.12.2017 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
22.12. - 22.12.2017 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.01. - 16.01.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.01. - 17.01.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.01. - 17.01.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.01. - 18.01.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.01. - 19.01.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.01. - 23.01.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.01. - 23.01.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.01. - 26.01.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
24.01. - 25.01.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.01. - 30.01.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.01. - 31.01.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
29.01. - 30.01.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.01. - 31.01.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.01. - 01.02.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.01. - 31.01.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.02. - 02.02.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.02. - 02.02.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.02. - 02.02.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
05.02. - 07.02.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
05.02. - 07.02.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
06.02. - 07.02.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.02. - 09.02.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.02. - 09.02.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.02. - 09.02.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.02. - 14.02.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
12.02. - 14.02.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
13.02. - 14.02.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.02. - 16.02.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.02. - 16.02.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.02. - 20.02.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.02. - 22.02.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.02. - 22.02.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.02. - 23.02.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
23.02. - 23.02.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.02. - 27.02.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.02. - 28.02.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.02. - 28.02.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.02. - 01.03.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.03. - 02.03.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.03. - 06.03.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.03. - 06.03.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.03. - 09.03.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
07.03. - 08.03.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.03. - 13.03.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.03. - 14.03.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.03. - 14.03.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.03. - 16.03.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.03. - 21.03.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
19.03. - 20.03.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.03. - 22.03.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.03. - 23.03.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.03. - 23.03.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.03. - 28.03.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
26.03. - 28.03.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.03. - 28.03.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.03. - 30.03.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.03. - 30.03.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.03. - 30.03.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.04. - 04.04.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 0.00 Add to cart
04.04. - 05.04.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.04. - 05.04.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.04. - 06.04.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
06.04. - 06.04.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
09.04. - 10.04.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.04. - 11.04.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.04. - 11.04.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.04. - 12.04.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.04. - 13.04.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.04. - 18.04.2018 09:00-17:00 Objektorientierte Programmierung mit MATLAB Mathworks so-logic (top1) (Austria) € 0.00 Add to cart
19.04. - 20.04.2018 09:00-17:00 Machine Learning mit MATLAB Mathworks so-logic (top1) (Austria) € 0.00 Add to cart
23.04. - 24.04.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.04. - 24.04.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.04. - 27.04.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
25.04. - 26.04.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.04. - 01.05.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.05. - 02.05.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.05. - 02.05.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
03.05. - 04.05.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.05. - 08.05.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.05. - 09.05.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
09.05. - 10.05.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.05. - 11.05.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.05. - 16.05.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.05. - 16.05.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.05. - 16.05.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.05. - 18.05.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.05. - 18.05.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.05. - 18.05.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.05. - 23.05.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.05. - 23.05.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
22.05. - 23.05.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.05. - 25.05.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.05. - 25.05.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.05. - 29.05.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.05. - 31.05.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.05. - 31.05.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.06. - 01.06.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.06. - 01.06.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
04.06. - 05.06.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.06. - 06.06.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.06. - 06.06.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.06. - 07.06.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.06. - 08.06.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.06. - 12.06.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.06. - 12.06.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.06. - 14.06.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.06. - 15.06.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
18.06. - 19.06.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.06. - 20.06.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.06. - 20.06.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
21.06. - 21.06.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.06. - 27.06.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
25.06. - 26.06.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.06. - 29.06.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.06. - 29.06.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.06. - 29.06.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.07. - 04.07.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.07. - 04.07.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.07. - 04.07.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.07. - 06.07.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.07. - 06.07.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.07. - 06.07.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.07. - 11.07.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.07. - 11.07.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
10.07. - 11.07.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.07. - 13.07.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.07. - 13.07.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.07. - 17.07.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.07. - 19.07.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.07. - 19.07.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.07. - 21.07.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.07. - 20.07.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
23.07. - 24.07.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.07. - 26.07.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.07. - 27.07.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.07. - 31.07.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.07. - 31.07.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.08. - 02.08.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.08. - 03.08.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
06.08. - 07.08.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.08. - 08.08.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.08. - 08.08.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
09.08. - 10.08.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.08. - 14.08.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.08. - 15.08.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
15.08. - 16.08.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.08. - 17.08.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.08. - 17.08.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.08. - 22.08.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
20.08. - 22.08.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.08. - 22.08.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.08. - 29.08.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.08. - 29.08.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
28.08. - 29.08.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.08. - 31.08.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.08. - 31.08.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.09. - 04.09.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.09. - 06.09.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.09. - 06.09.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.09. - 07.09.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
07.09. - 07.09.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
10.09. - 11.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.09. - 12.09.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.09. - 12.09.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.09. - 13.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.09. - 14.09.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.09. - 18.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.09. - 18.09.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.09. - 20.09.2018 09:00-17:00 MATLAB Grundlagen Mathworks so-logic (top1) (Austria) € 0.00 Add to cart
18.09. - 20.09.2018 09:00-17:00 MATLAB Grundlagen Mathworks so-logic (top1) (Austria) € 0.00 Add to cart
19.09. - 21.09.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
19.09. - 20.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.09. - 25.09.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.09. - 26.09.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.09. - 26.09.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.10. - 03.10.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
01.10. - 02.10.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.10. - 04.10.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.10. - 05.10.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.10. - 05.10.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
08.10. - 11.10.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
08.10. - 10.10.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.10. - 10.10.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.10. - 17.10.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.10. - 17.10.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.10. - 17.10.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.10. - 19.10.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.10. - 19.10.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 25.10.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.10. - 25.10.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
29.10. - 31.10.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.10. - 31.10.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.10. - 31.10.2018 09:00-17:00 Designing with the UltraScale Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.10. - 01.11.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.11. - 02.11.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.11. - 06.11.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
05.11. - 06.11.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.11. - 09.11.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
07.11. - 08.11.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.11. - 11.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
12.11. - 13.11.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.11. - 14.11.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.11. - 14.11.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.11. - 16.11.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.11. - 20.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.11. - 21.11.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
21.11. - 22.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.11. - 23.11.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.11. - 23.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.11. - 27.11.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
26.11. - 28.11.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.11. - 28.11.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 0.00 Add to cart
03.12. - 05.12.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.12. - 05.12.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.12. - 05.12.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.12. - 07.12.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.12. - 07.12.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.12. - 11.12.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.12. - 13.12.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.12. - 13.12.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 14.12.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.12. - 14.12.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart