Training schedules 2022-05-19 - 2023-05-19

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Event period Training Partner Location Price
23.05. - 23.05.2022 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
23.05. - 23.05.2022 09:00-17:00 Vision KRIA SOM Xilinx so-logic (top1) (Austria) € 0.00 Add to cart
23.05. - 24.05.2022 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.05. - 25.05.2022 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
24.05. - 25.05.2022 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.05. - 27.05.2022 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.05. - 27.05.2022 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.05. - 30.05.2022 09:00-17:00 Vision KRIA SOM Xilinx so-logic (top1) (Austria) € 0.00 Add to cart
13.06. - 14.06.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.06. - 15.06.2022 09:00-17:00 Zynq All Programmable SoC System Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.06. - 16.06.2022 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.06. - 16.06.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.06. - 17.06.2022 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
17.06. - 17.06.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.06. - 21.06.2022 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.06. - 22.06.2022 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
22.06. - 23.06.2022 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.06. - 24.06.2022 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.06. - 27.06.2022 09:00-17:00 Vision KRIA SOM Xilinx so-logic (top1) (Austria) € 0.00 Add to cart
27.06. - 28.06.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.06. - 30.06.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.07. - 05.07.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.07. - 06.07.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.07. - 08.07.2022 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.07. - 13.07.2022 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.07. - 22.07.2022 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.07. - 26.07.2022 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.07. - 28.07.2022 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.08. - 01.08.2022 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.08. - 03.08.2022 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.08. - 05.08.2022 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.08. - 05.08.2022 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.08. - 09.08.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.08. - 10.08.2022 09:00-17:00 Zynq All Programmable SoC System Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.08. - 11.08.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.08. - 11.08.2022 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.08. - 12.08.2022 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.08. - 12.08.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
12.08. - 12.08.2022 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.08. - 16.08.2022 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.08. - 17.08.2022 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
17.08. - 18.08.2022 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.08. - 19.08.2022 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.08. - 23.08.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.08. - 25.08.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.08. - 30.08.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.09. - 02.09.2022 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.09. - 01.09.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.09. - 13.09.2022 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.09. - 16.09.2022 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.09. - 27.09.2022 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.09. - 30.09.2022 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.10. - 03.10.2022 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
03.10. - 05.10.2022 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.10. - 05.10.2022 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.10. - 07.10.2022 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.10. - 07.10.2022 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.10. - 11.10.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2022 09:00-17:00 Zynq All Programmable SoC System Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.10. - 13.10.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.10. - 13.10.2022 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.10. - 14.10.2022 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.10. - 14.10.2022 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.10. - 14.10.2022 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
17.10. - 18.10.2022 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.10. - 19.10.2022 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
20.10. - 21.10.2022 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.10. - 21.10.2022 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 26.10.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.10. - 28.10.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.11. - 02.11.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.11. - 03.11.2022 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.11. - 11.11.2022 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.11. - 22.11.2022 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.11. - 25.11.2022 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
28.11. - 29.11.2022 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2022 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.12. - 14.12.2022 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
12.12. - 12.12.2022 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.12. - 15.12.2022 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.12. - 16.12.2022 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.12. - 16.12.2022 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart