Training schedules 2024-11-04 - 2025-11-04
Event period | Training | Partner | Location | Price | |
---|---|---|---|---|---|
06.11. - 07.11.2024 09:00-17:00 | Designing with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
10.11. - 11.11.2024 09:00-17:00 | Verification with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
11.11. - 11.11.2024 09:00-17:00 | AMD Versal Compendium 3 : AI Engine | so-logic | so-logic (top1) (Austria) | € 0.00 | |
11.11. - 15.11.2024 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
12.11. - 13.11.2024 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
18.11. - 22.11.2024 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
25.11. - 29.11.2024 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
02.12. - 03.12.2024 09:00-17:00 | Designing with Versal AI Engine: Architecture and Design Flow - 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
02.12. - 06.12.2024 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
04.12. - 06.12.2024 09:00-17:00 | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2 | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
09.12. - 11.12.2024 09:00-17:00 | Designing with Versal AI Engine: Kernel Programming and Optimization - 3 | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
09.12. - 13.12.2024 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
12.12. - 13.12.2024 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
12.12. - 16.12.2024 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
16.12. - 19.12.2024 09:00-17:00 | Designing with the Versal Adaptiv SOC: Design Methodology | Xilinx | so-logic (top1) (Austria) | € 3,200.00 | |
20.12. - 20.12.2024 09:00-17:00 | Designing with the Versal Adaptive SoC: Network on Chip | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
01.01. - 01.01.2025 09:00-17:00 | Adaptive SoCs for System Architects | Xilinx | Virtual Learning Environment (Online) | € 1,600.00 | |
07.01. - 09.01.2025 09:00-17:00 | Designing with VHDL | Xilinx | Virtual Learning Environment (Online) | € 2,550.00 | |
07.01. - 08.01.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.01. - 10.01.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
13.01. - 14.01.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 0.00 | |
15.01. - 16.01.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.02. - 10.02.2025 09:00-16:00 | C++ for Adaptive SOC | Xilinx | so-logic (top1) (Austria) | € 0.00 | |
15.04. - 17.04.2025 09:00-17:00 | Designing with VHDL | Xilinx | Virtual Learning Environment (Online) | € 2,250.00 |