Training schedules 2018-06-23 - 2019-06-23

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Event period Training Partner Location Price
25.06. - 26.06.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.06. - 27.06.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
28.06. - 29.06.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.06. - 29.06.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.06. - 29.06.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.07. - 04.07.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.07. - 04.07.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.07. - 04.07.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.07. - 06.07.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.07. - 06.07.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.07. - 06.07.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.07. - 11.07.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.07. - 11.07.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
10.07. - 11.07.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.07. - 13.07.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.07. - 13.07.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.07. - 17.07.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.07. - 19.07.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.07. - 19.07.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.07. - 21.07.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.07. - 20.07.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
23.07. - 24.07.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2018 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.07. - 26.07.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.07. - 27.07.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.07. - 31.07.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.07. - 31.07.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.08. - 03.08.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
01.08. - 02.08.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.08. - 07.08.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.08. - 08.08.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.08. - 08.08.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
09.08. - 10.08.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.08. - 15.08.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
13.08. - 14.08.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.08. - 16.08.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.08. - 17.08.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.08. - 17.08.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.08. - 22.08.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
20.08. - 22.08.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.08. - 22.08.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.08. - 24.08.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.08. - 29.08.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.08. - 29.08.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
28.08. - 29.08.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.08. - 31.08.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.08. - 31.08.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.09. - 04.09.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.09. - 06.09.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.09. - 06.09.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.09. - 07.09.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
07.09. - 07.09.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
10.09. - 11.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.09. - 12.09.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.09. - 12.09.2018 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.09. - 13.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.09. - 14.09.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.09. - 18.09.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.09. - 18.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.09. - 20.09.2018 09:00-17:00 MATLAB Grundlagen Mathworks so-logic (top1) (Austria) € 0.00 Add to cart
18.09. - 20.09.2018 09:00-17:00 MATLAB Grundlagen Mathworks so-logic (top1) (Austria) € 0.00 Add to cart
19.09. - 20.09.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.09. - 21.09.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
24.09. - 25.09.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.09. - 26.09.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.09. - 26.09.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.10. - 02.10.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.10. - 03.10.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
03.10. - 04.10.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.10. - 05.10.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.10. - 05.10.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
08.10. - 11.10.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
08.10. - 10.10.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.10. - 10.10.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.10. - 12.10.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.10. - 17.10.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.10. - 17.10.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.10. - 17.10.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.10. - 19.10.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.10. - 19.10.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 25.10.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.10. - 25.10.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
29.10. - 31.10.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.10. - 31.10.2018 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.10. - 31.10.2018 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.10. - 01.11.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.11. - 02.11.2018 09:00-17:00 Zynq-7000 All Programmable SoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.11. - 06.11.2018 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.11. - 06.11.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.11. - 09.11.2018 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
07.11. - 08.11.2018 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.11. - 11.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
12.11. - 13.11.2018 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.11. - 14.11.2018 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.11. - 14.11.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.11. - 16.11.2018 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.11. - 20.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.11. - 21.11.2018 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
21.11. - 22.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.11. - 23.11.2018 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.11. - 23.11.2018 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.11. - 27.11.2018 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
26.11. - 28.11.2018 09:00-17:00 Signal Integrity and Board Design for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.11. - 28.11.2018 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2018 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2018 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.11. - 30.11.2018 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.12. - 05.12.2018 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.12. - 05.12.2018 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.12. - 05.12.2018 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.12. - 07.12.2018 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.12. - 07.12.2018 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.12. - 11.12.2018 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.12. - 13.12.2018 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.12. - 13.12.2018 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 14.12.2018 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.12. - 14.12.2018 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart