Training schedules 2020-09-19 - 2021-09-19

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Event period Training Partner Location Price
28.09. - 29.09.2020 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.10. - 02.10.2020 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.10. - 07.10.2020 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
05.10. - 05.10.2020 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
06.10. - 07.10.2020 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.10. - 09.10.2020 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.10. - 09.10.2020 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.10. - 13.10.2020 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.10. - 14.10.2020 09:00-17:00 Zynq All Programmable SoC System Architecture Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.10. - 15.10.2020 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.10. - 15.10.2020 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.10. - 16.10.2020 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.10. - 16.10.2020 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
16.10. - 16.10.2020 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
19.10. - 20.10.2020 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.10. - 21.10.2020 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
22.10. - 23.10.2020 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.10. - 23.10.2020 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.10. - 28.10.2020 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.10. - 30.10.2020 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.11. - 04.11.2020 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.11. - 05.11.2020 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
09.11. - 10.11.2020 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.11. - 24.11.2020 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.11. - 27.11.2020 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
30.11. - 01.12.2020 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.12. - 03.12.2020 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.12. - 14.12.2020 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.12. - 16.12.2020 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.12. - 18.12.2020 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.12. - 18.12.2020 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.12. - 18.12.2020 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.01. - 05.01.2021 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.01. - 05.01.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.01. - 12.01.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.01. - 15.01.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
18.01. - 19.01.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.01. - 21.01.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.01. - 25.01.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.01. - 27.01.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
26.01. - 27.01.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.02. - 05.02.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.03. - 16.03.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.03. - 19.03.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
22.03. - 23.03.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.03. - 26.03.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.03. - 31.03.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
29.03. - 29.03.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
30.03. - 31.03.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.04. - 07.04.2021 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.04. - 08.04.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.05. - 11.05.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.05. - 14.05.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
18.05. - 19.05.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.05. - 26.05.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
24.05. - 25.05.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.05. - 24.05.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.05. - 26.05.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.06. - 17.06.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.07. - 20.07.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.07. - 23.07.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.07. - 27.07.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.07. - 29.07.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.08. - 02.08.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.08. - 04.08.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
11.08. - 12.08.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.08. - 13.08.2021 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.09. - 14.09.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.09. - 17.09.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
27.09. - 28.09.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.09. - 01.10.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.10. - 06.10.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
04.10. - 04.10.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
05.10. - 06.10.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.10. - 14.10.2021 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.10. - 15.10.2021 09:00-17:00 Designing with the Zynq UltraScale+ RFSoC Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.11. - 23.11.2021 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.11. - 26.11.2021 09:00-17:00 Developing AWS F1 Applications Using the SDAccel Environment Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
29.11. - 30.11.2021 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.11. - 01.12.2021 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.12. - 15.12.2021 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
13.12. - 13.12.2021 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.12. - 16.12.2021 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart