Designing FPGAs Using the Vivado Design Suite 4

Learn how to use the advanced aspects of the Vivado™ Design Suite. The focus is on: Applying techniques to reduce delay and to improve clock skew and clock uncertainty Utilizing floorplanning techniques Employing advanced implementation options Utilizing AMD security features Identifying advanced FPGA configurations Debugging a design at the device startup phase Utilizing Tcl scripting when using the Vivado logic analyzer in a design

Course Description

This course teaches how to use the advanced aspects of the Vivado™ Design Suite. It covers techniques to reduce delay, improve clock skew and clock uncertainty, utilize floorplanning methods, apply advanced implementation options, use AMD security features, identify advanced FPGA configurations, debug a design during device startup, and employ Tcl scripting with the Vivado logic analyzer.

The emphasis of this course is on:

• Applying techniques to reduce delay and improve clock skew and clock uncertainty
• Utilizing floorplanning techniques
• Employing advanced implementation options
• Utilizing AMD security features
• Identifying advanced FPGA configurations
• Debugging a design at the device startup phase
• Utilizing Tcl scripting when using the Vivado logic analyzer

Training Duration

21 hours

Additional Information

• Number of Chapters: 27
• Number of Labs: 10
• Number of Demos: 1
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• UltraFast Design Methodology – Timing Closure

Chapter 2

• Hierarchical Design

Chapter 3

• Incremental Compile Flow

Chapter 4

• AMD Vivado™ Design Suite ECO Flow

Chapter 5

• Managing IP in Remote Locations

Chapter 6

• Timing Closure Using Physical Optimization Techniques

Chapter 7

• Reducing Logic Delay

Chapter 8

• Reducing Net Delay – Introduction

Chapter 9

• Improving Clock Skew

Chapter 10

• Improving Clock Uncertainty

Chapter 11

• Intelligent Design Runs

Chapter 12

• Power Management Techniques

Chapter 13

• Introduction to Floorplanning

Chapter 14

• Design Analysis and Floorplanning

Chapter 15

• Congestion

Chapter 16

• Daisy Chains and Gangs in Configuration

Chapter 17

• Bitstream Security

Chapter 18

• Vivado Design Suite Debug Methodology

Chapter 19

• Trigger and Debug at Device Startup

Chapter 20

• Trigger Using the Trigger State Machine in the Vivado Logic Analyzer

Chapter 21

• Introduction to the Vivado Store

Chapter 22

• Debugging the Design Using Tcl Commands

Chapter 23

• Using Procedures in Tcl Scripting

Chapter 24

• Using Lists in Tcl Scripting

Chapter 25

• Using Regular Expressions in Tcl Scripting

Chapter 26

• Debugging and Error Handling in Tcl Scripts

Chapter 27

• Designing FPGAs Using the Vivado Design Suite 4 Full Course Quiz