DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite

FPGA-DFX

Course Description

This course teaches how to construct, implement, and download a Dynamic Function eXchange (DFX) design using the Vivado™ Design Suite. It covers the complete tool flow and mechanics required to successfully create DFX designs for AMD FPGAs and adaptive SoCs.

The emphasis of this course is on:

  • Identifying best design practices and understanding the subtleties of the DFX design flow
  • Using DFX in AMD FPGAs and adaptive SoCs
  • Implementing DFX designs using features such as block design containers (BDC), Abstract Shells, and nested DFX
  • Recognizing DFX design considerations for FPGAs and adaptive SoCs
  • Using the DFX IPs in the DFX process
  • Analyzing and floorplanning DFX designs
  • Configuring devices using DFX
  • Applying appropriate debugging techniques on DFX designs
  • Implementing DFX in an embedded system environment

Training Duration

29 hours

Additional Information

  • Number of Chapters: 23
  • Number of Labs: 11
  • Number of Demos: 0
  • Current Version: 2025.2

What's New

  • Updated DFX Design Considerations for All AMD Devices module with information on Embedded I/O usage guidelines and initializing reconfigurable modules after DFX
  • All labs have been updated to the latest software versions

Chapters

Chapter 1

  • Introduction to Dynamic Function eXchange (DFX)

Chapter 2

  • DFX Flow Using the Vivado Design Suite GUI

Chapter 3

  • DFX Flow Using Vivado Design Suite Tcl Commands

Chapter 4

  • DFX for the Versal Architecture

Chapter 5

  • DFX Block Design Containers in the Vivado IP Integrator

Chapter 6

  • Abstract Shell for Dynamic Function eXchange

Chapter 7

  • RTL Modular NoC Flow for Versal DFX Designs

Chapter 8

  • Nested DFX

Chapter 9

  • DFX Design Considerations for All AMD Devices

Chapter 10

  • DFX Design Considerations for 7 Series, Zynq SoC, UltraScale, and UltraScale+ Devices

Chapter 11

  • DFX Design Considerations for Versal Devices

Chapter 12

  • DFX Intellectual Property (IP)

Chapter 13

  • Floorplanning a DFX Design

Chapter 14

  • Floorplanning for Versal Devices

Chapter 15

  • DFX Timing Analysis and Constraints

Chapter 16

  • Configuring Devices Using DFX

Chapter 17

  • Configuration Parameters

Chapter 18

  • DFX Bitstreams and PDIs

Chapter 19

  • DFX Bitstream Integrity

Chapter 20

  • DFX Debugging

Chapter 21

  • DFX in Embedded Systems

Chapter 22

  • DFX Designs Using the PCIe Core

Chapter 23

  • Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite Full Course Quiz

Event Schedule

Virtual Learning Environment (Online)
  • 11.11. - 12.11.2027 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
  • 10.05. - 11.05.2027 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
  • 20.08. - 21.08.2026 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
Request on-demand event: Click here.

Partner

Xilinx
Updated at: 2026-07-08 11:15:43 +0200to the top