FPGA Design with High Level Synthesis HLS Basic

Course Description

"Basic HLS Tutorial" is a document made for beginners who are entering the world of embedded system design using FPGAs.This tutorial explains, step by step, the procedure of designing a simple digital system using C/C++/SystemC languages and Xilinx Vivado Design Suite.

Release Date

July 2022

Training Duration

2 days

Purpose of this Tutorial

This tutorial is made to introduce you how to create, simulate and test an project and run it on your development board.

The following project is designed for:

  • Designing Surface: VIVADO 2021.2
  • Programming Language: C
  • Device: Sozius Development Board

After completing this tutorial, you will be able to:

  • Launch and navigate the Vivado High-Level Synthesis (HLS) tool
  • Create a project using New Project Creation Wizard
  • Develop a C algorithm for your design
  • Verify a C algorithm of your design
  • Synthesize a C algorithm into an RTL implementation (High-Level Synthesis)
  • Generate reports and analyze the design
  • Verify the RTL implementation
  • Package the RTL implementations

Event Schedule

so-logic (top1) (Austria)
  • 21.11. - 22.11.2022 09:00-17:00 — € 1,600.00 excl. VAT Add to cart
  • 13.03. - 14.03.2023 09:00-17:00 — € 1,600.00 excl. VAT Add to cart

Partner

so-logic
Updated at: 2022-07-05 13:11:39 +0200to the top