FPGA Design with High Level Synthesis (HLS) Basic

Course Description

"Basic HLS Tutorial" is a document made for beginners who are entering the world of embedded system design using FPGAs.This tutorial explains, step by step, the procedure of designing a simple digital system using C/C++/SystemC languages and AMD Xilinx Vivado Design Suite.

In the "Basic HLS Tutorial", a PWM signal modulated using the sine wave with two different frequencies (1 Hz and 3.5Hz) will be created. Frequency that will be chosen depends on the position of the two-state on-board switch.

Release Date

July 2022

Training Duration

2 days

Purpose of this Tutorial

This tutorial is made to introduce you how to create, simulate and test an project and run it on your development board.

The following project is designed for:

  • Designing Surface: VIVADO 2022.2
  • Programming Language: C
  • Device: Sozius Development Board

After completing this tutorial, you will be able to:

  • Launch and navigate the Vivado High-Level Synthesis (HLS) tool
  • Create a project using New Project Creation Wizard
  • Develop a C algorithm for your design
  • Verify a C algorithm of your design
  • Synthesize a C algorithm into an RTL implementation (High-Level Synthesis)
  • Generate reports and analyze the design
  • Verify the RTL implementation
  • Package the RTL implementations

Lab Descriptions

  • Lab 1: "Introduction"
  • Lab 2: "About HLS Tool"
  • Lab 3: "Developing Custom IP Core using HLS"
  • Lab 4: "Using Developed IP Core in Vivado Design Suite"

Event Schedule

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Updated at: 2023-03-22 16:04:20 +0100to the top