FPGA Design with VHDL Basic

Course Description

"Basic FPGA Tutorial" is a document made for beginners who are entering the FPGA world. This tutorial explains, step by step, the procedure of designing a simple digital system using VHDL language and Xilinx Vivado Design Suite.

Release Date

July 2022

Training Duration

3 days

Purpose of this Tutorial

This tutorial is made to introduce you how to create, simulate and test an project and run it on your

The following project is designed for:

  • Designing Surface: VIVADO 2021.2
  • HD Language: VHDL
  • Simulator: Vivado Simulator
  • Device: Sozius Development Board

After completing this tutorial, you will be able to:

  • Launch and navigate the Vivado Integrated Design Environment (IDE)
  • Learn the various types of projects that can be created with the New Project Creation Wizard • Create and add design source files with the Vivado IDE
  • Synthesize and implement the design in the Vivado IDE
  • Simulate a design using integrated Vivado Simulator
  • Run your design on the target development board
  • Debug a design in hardware using Vivado Logic Analyzer • Designing with IPs

Structure of this Tutorial

  • Chapter 1: "Introduction" - In this chapter you will find what is the purpose of this tutorial, expla- nation what is the PWM signal, block diagram of one possible solution for the modulator design and a lot of basic information about the Vivado Design Suite.
  • Chapter 2: "Selector" - In this chapter you will find all the necessary information about how to create a new project in the Vivado IDE, how to create SElector module as constituent part of the Modulator design, how to generate its test bench file and how to simulate it with the integrated Vivado simulator.
  • Chapter 3: "Counter" - This chapter explains how to create Counter module, how to create its test bench file and how to simulate it with Vivado simulator.
  • Chapter 4: "Sine Package" - This chapter holds the information how to create Sine package as one universal package that will be used in almost all modules of the Modulator design.
  • Chapter 5: "Digital Sine" - This chapter explains how to create Digital Sine module, how to create its test bench file and how to simulate it with Vivado simulator.
  • Chapter 6: "PWM" - This chapter explains how to create PWM module. This module will generate an PWM signal modulated using the digital sine wave from the Digital Sine module. In this chapter you will find how to create its FSM state diagram, its test bench file and how to simulate it with Vivado simulator.
  • Chapter 7: "Modulator" - This chapter includes all the necessary information about the Modulator module, as the top module of our design. In this chapter you will find information how to create Modulator module and its test bench file and how to simulate it with Vivado simulator. Additionally, this chapter holds information about the Vivado synthesis process.
  • Chapter 8: "Modulator Sozius Wrapper" - This chapter includes all the necessary information about the Modulator Sozius Wrapper module. This module will be used to target Sozius development board. Considering that the main component of the Sozius development board is Zynq-7000 AP SoC, in this chapter you will find all the necessary information how to use PS and PL parts of the Zynq-7000 AP SoC system for the purpose of our project.
  • Chapter 9: "Design Implementation" - This is a large chapter and includes all the information about the design implementation process steps. In this chapter you will learn how to create XDC file, how to implement your design, how to generate bitstream file and how to program your device. Here you will also find information about the necessary modifications in case of using different development boards.
  • Chapter 10: "Debugging Design" - This chapter explains the process of debugging design. In this chapter you will find the information how to instantiate ILA and VIO cores into the design and how to debug your design using integrated Vivado Logic Anayzer.
  • Chapter 11: "Debugging with IPs" - This chapter explains how you can create Modulator design using your own IPs, with the help of the Vivado IP Packager and IP Integrator tools, how you can debug IP integrated designs and how you can create new Modulator IP core with AXI4 interface in it.
  • Chapter 12: "Working with Partial Reconfiguration Flow" - This chapter explains how you can work with Partial Reconfiguration Flow, which allows reconfiguration of modules within an active design.

This tutorial is accompanied by the pdf lab presentations. In total there are 16 labs. Correlation between labs and this tutorial document is the following:

  • Lab 1: "Introduction" - covers the information presented in the Chapter 1: "Introduction" of this tutorial.
  • Lab 2: "Quick Guide to Running Modulator Design on FPGA Board" - presents the overview of design development using Xilinx Vivado Design Suite and VHDL modelling language. Therefore, this lab covers information located throughout the whole tutorial document.
  • Lab 3: "Creating Selector Module" - covers the information presented in the sub-chapters 2.1, 2.2, 2.4, 2.4.1 of Chapter 2: "Selector" of this tutorial.
  • Lab 4: "Selector Verification" - covers the information presented in the sub-chapters 2.5, 2.6 of Chapter 2: "Selector" of this tutorial.
  • Lab 5: "Creating Counter Module" - covers the information presented in the Chapter 3: "Counter"of this tutorial.
  • Lab 6: "Creating Sine Package" - covers the information presented in the Chapter 4: "SinePackage" of this tutorial.
  • Lab 7: "Creating Digital Sine Module" - covers the information presented in the Chapter 5: Digital Sine" of this tutorial.
  • Lab 8: "Creating PWM Module" - covers the information presented in the Chapter 6: "PWM"of this tutorial.
  • Lab 9: "Creating Modulator Module" - covers the information presented in the Chapter 7: "Mod-ulator" of this tutorial.
  • Lab 10: "Creating Modulator Sozius Wrapper Module" - covers the information presented in the Chapter 8: "Modulator Sozius Wrapper" of this tutorial.
  • Lab 11: "Creating XDC File" - covers the information presented in the sub-chapter 9.1 of Chapter 9: "Design Implementation" of this tutorial.
  • Lab 12: "Design Implementation" - covers the information presented in the sub-chapter 7.5 of Chapter 7: "Modulator" and sub-chapters 9.2, 9.3, 9.4 of Chapter 9: "Design Implementa-tion" of this tutorial.
  • Lab 13: "Debugging Design" - covers the information presented in the sub-chapter 10.1 of the Chapter 10 "Debugging Design" of this tutorial.
  • Lab 14: "Debug a Design using Integrated Vivado Logic Analyzer" - covers the information presented in the sub-chapter 10.2 of the Chapter 10 "Debugging Design" of this tutorial.
  • Lab 15: "Designing with IPs - IP Integrator" - covers the information presented in the sub-chapter 11.1 of the Chapter 11 " Designing with IPs" of this tutorial.
  • Lab 16: "Creating Modulator IP with AXI4 Interface" - covers the information presented in the sub-chapter 11.2 of the Chapter 11 " Designing with IPs" of this tutorial.
  • Lab 17: "Working with Partial Reconfiguration Flow" - covers the information presented in the sub-chapters 12.1 and 12.2 of the Chapter 12 "Working with Partial Reconfiguration Flow" of this tutorial.

Event Schedule

so-logic (top1) (Austria)
  • 05.10. - 07.10.2022 09:00-17:00 — € 2,400.00 excl. VAT Add to cart
  • 12.12. - 14.12.2022 09:00-17:00 — € 2,400.00 excl. VAT Add to cart
  • 27.03. - 29.03.2023 09:00-17:00 — € 2,400.00 excl. VAT Add to cart
  • 30.05. - 01.06.2023 09:00-17:00 — € 2,400.00 excl. VAT Add to cart

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Updated at: 2022-07-05 14:10:48 +0200to the top