Designing an Integrated PCI Express System

En

Course Description

Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Release Date

June 2017

Level

Connectivity 3

Training Duration

2 days

Who Should Attend?

  • Hardware designers who want to create applications using Xilinx IP cores for PCI Express
  • Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
  • System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

Prerequisites

  • Experience with PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Some experience with Xilinx implementation tools
  • Some experience with a simulation tool, preferably the Vivado® simulator
  • Moderate digital design experience

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Construct a basic PCIe system by:
    • Selecting the appropriate core for your application
    • Specifying requirements of an endpoint application
    • Connecting this endpoint with the core
    • Utilizing FPGA resources to support the core
    • Simulating the design
  • Identify the advanced capabilities of the PCIe specification protocol and feature set

Course Outline

Day 1

  • Course Introduction
  • Lab 0: Packet Coding
  • Xilinx PCI Express Solutions
  • Connecting Logic to the Core – AXI Interface
  • PCIe Core Customization
  • Lab 1: Constructing the PCIe Core
  • Packet Formatting Details
  • Simulating a PCIe System Design
  • Lab 2: Simulating the PCIe Core
  • Endpoint Application Considerations
  • PCI Express in Embedded Systems

Day 2

  • Lab 3: Using the PCI Express Core in IP Integrator
  • Application Focus: DMA
  • Design Implementation and PCIe Configuration
  • Lab 4: Implementing the PCIe Design
  • Root Port Applications
  • Debugging and Compliance
  • Lab 5: Debugging the PCIe Design
  • Interrupts and Error Management
  • Course Summary

Lab Descriptions

  • Lab 0: Packaet Coding – This lab helps you recall basic PCI Express transaction layer packet formats.
  • Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
  • Lab 2: Simulating the PCIe Core – This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.
  • Lab 3: Using the PCI Express Core in IP Integrator – This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.
  • Lab 4: Implementing the PCIe Design – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.
  • Lab 5: Debugging the PCIe Design – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.

Event Schedule

so-logic (top1) (Austria)
  • 14.02. - 15.02.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 04.04. - 05.04.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 16.05. - 17.05.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 22.08. - 23.08.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 10.10. - 11.10.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 28.11. - 29.11.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
so-logic (Brazil)
  • 11.07. - 12.07.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2018-11-11 13:55to the top