Designing with Versal AI Engine 1: Architecture and Design Flow

This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...

Course Description

This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), and how to analyze a kernel program by using various debugger features.

The emphasis of this course is on:

• Describing the AI Engine (AIE) architecture
• Illustrating the Versal AI Engine tool flow
• Reviewing the data movement between AI Engines, via memory and DMA, and between AI Engines and programmable logic (PL)
• Designing with single AI Engine kernels and analyzing scalar and vectorized kernel performance using the Vitis™ unified software platform
• Describing adaptive data flow graphs and designing with multiple AI Engine kernels using the Vitis Unified IDE
• Analyzing and debugging kernel performance
• Describing the AIE‑ML architecture
• Illustrating the programming model for AIE‑ML
• Describing the AIE‑ML v2 architecture for Versal AI Edge Series Gen 2 devices

Training Duration

22 hours

Additional Information

• Number of Labs: 6
• Number of Chapters: 18
• Current Version: 2025.2
• Number of Demos: 0

What's New

• AMD Versal AI Engine Tool Flow module: Added additional information on using the Vitis environment in the design flow
• All labs updated to the latest software versions

Chapters

Chapter 1

• Overview of the AMD Versal Adaptive SoC Architecture

Chapter 2

• AMD Versal AI Engine Architecture

Chapter 3

• AI Engine Interfaces

Chapter 4

• AMD Versal AI Engine Memory and Data Movement

Chapter 5

• Versal Adaptive SoC: Application Partitioning and Mapping

Chapter 6

• AMD Versal AI Engine Tool Flow

Chapter 7

• Scalar and Vector Data Types

Chapter 8

• AI Engine APIs

Chapter 9

• Buffers and Streaming Data APIs

Chapter 10

• Analyzing AI Engine Design Reports Using the Vitis Unified IDE

Chapter 11

• The Programming Model – Single Kernel

Chapter 12

• The Programming Model – Single Kernel Using Vector Data Types

Chapter 13

• The Programming Model – Introduction to the Adaptive Data Flow (ADF) Graph

Chapter 14

• The Programming Model – Multiple Kernels Using Graphs

Chapter 15

• Introduction to the AIE‑ML Architecture

Chapter 16

• AIE‑ML Memory Tiles and Programming

Chapter 17

• Introduction to the AIE‑MLv2 Architecture

Chapter 18

• Designing with Versal AI Engine – Architecture and Design Flow Full Course Quiz