High-Level Synthesis with Vitis HLS

This course provides a thorough introduction to high-level synthesis (HLS) using the AMD Vitis™ Unified IDE.The focus of this course is on:Converting C/C++ designs into RTL implementationsLearning the HLS component de...

Course Description

This course introduces high-level synthesis (HLS) using the AMD Vitis Unified IDE. It covers converting C/C++ designs into RTL implementations, learning the HLS component development flow, creating I/O interfaces, applying optimization techniques, improving throughput, area, latency, and logic using HLS pragmas and directives, exporting IP for use with the Vivado IP catalog, and migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE.

The emphasis of this course is on:

• Converting C/C++ designs into RTL implementations
• Learning the HLS component development flow
• Creating I/O interfaces for designs
• Applying optimization techniques
• Improving throughput, area, latency, and logic using HLS pragmas/directives
• Exporting IP for use with the Vivado IP catalog
• Migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE

Training Duration

26 hours

Additional Information

• Number of Chapters: 24
• Number of Labs: 12
• Number of Demos: 0
• Current Version: 2025.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• Introduction to High-Level Synthesis

Chapter 2

• HLS Component Development Flow

Chapter 3

• Abstract Parallel Programming Model for HLS

Chapter 4

• Design Exploration with Directives

Chapter 5

• HLS Component Development Using the Command Line

Chapter 6

• Introduction to Vitis HLS Design Methodology

Chapter 7

• Introduction to I/O Interfaces

Chapter 8

• Block-Level Protocols

Chapter 9

• Port-Level I/O Protocols

Chapter 10

• AXI Adapter Interface Protocols

Chapter 11

• Optimizing for Performance: PIPELINE

Chapter 12

• Optimizing for Performance – DATAFLOW

Chapter 13

• Optimizing for Throughput

Chapter 14

• Optimizing for Latency Default Behavior

Chapter 15

• Optimizing for Latency – Reducing Latency

Chapter 16

• Optimizing for Area and Logic

Chapter 17

• Optimizing AXI System Performance

Chapter 18

• Vitis HLS Performance Pragma

Chapter 19

• Vitis HLS Libraries

Chapter 20

• Vitis HLS Libraries: Arbitrary Precision Data Types

Chapter 21

• Using Pointers in Vitis HLS

Chapter 22

• HLS Component Design Flow – System Integration

Chapter 23

• Migrating to the Vitis Unified IDE – HLS Component

Chapter 24

• High-Level Synthesis with the Vitis Unified IDE Full Course Quiz