Embedded Heterogeneous Design

This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project to design an embedded heterogeneous system usin...

Course Description

This course covers AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components, integrating them into an embedded heterogeneous system using v++ tools and the AMD Vitis™ Unified IDE. It provides a complete overview of heterogeneous system design, partitioning, mapping, development, analysis, debugging, and subsystem integration.

The emphasis of this course is on:

• Describing an embedded heterogeneous system design
• Illustrating AMD Versal adaptive SoC architecture, NoC, and AI Engine
• Describing an AMD Versal design tool flow
• Developing HLS and AIE components using AMD Vitis tools
• Utilizing v++ command line tools for compilation, linking, and packaging for emulation
• Demonstrating system design flow for heterogeneous embedded systems using the AMD Vitis Unified IDE

Training Duration

27 hours

Additional Information

• Number of Chapters: 17
• Number of Labs: 7
• Number of Demos: 0
• Current Version: 2025.2

What's New

• Tool Flow for Heterogeneous Systems module: Added information on using the Vitis environment in the design flow
• Embedded Heterogeneous System Design Flow module: Added information on Vitis Integrated flow, Vivado™ export flow, and Vitis Subsystem Simulation flow
• All labs updated to the latest software versions

Chapters

Chapter 1

• Introduction to Embedded Heterogeneous Design

Chapter 2

• AMD Versal Adaptive SoC: Architecture Overview

Chapter 3

• AMD Versal Adaptive SoC: NoC Architecture

Chapter 4

• Introduction to the AMD Versal AI Engine Architecture

Chapter 5

• Versal Adaptive SoC: Application Partitioning and Mapping

Chapter 6

• Driving the AMD Vitis Unified IDE – EHD

Chapter 7

• Tool Flow for Heterogeneous Systems

Chapter 8

• Introduction to AMD Vitis High-Level Synthesis Components

Chapter 9

• Vitis HLS Methodology and Optimization Techniques

Chapter 10

• AI Engine Programming – Kernels and Graphs

Chapter 11

• AI Engine System Partitioning Methodology

Chapter 12

• Analyzing AI Engine Design Reports Using the Vitis Unified IDE

Chapter 13

• Versal AI Engine Application Debug and Event Trace

Chapter 14

• Development Using the v++ Command Line Tools

Chapter 15

• Custom Platform Development

Chapter 16

• Embedded Heterogeneous System Design Flow

Chapter 17

• Embedded Heterogeneous Design – Full Course Quiz