Designing with Verilog

This course provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and b...

Course Description

This course provides a thorough introduction to the Verilog language. It covers writing efficient hardware designs, performing high-level HDL simulations, employing structural, register transfer level (RTL), and behavioral coding styles, targeting AMD devices and FPGA devices in general, and utilizing best coding practices. The course includes Verilog 1995 and Verilog 2001.

The emphasis of this course is on:

• Writing efficient hardware designs
• Performing high-level HDL simulations
• Employing structural, RTL, and behavioral coding styles
• Targeting AMD devices and FPGA devices
• Utilizing best coding practices

Training Duration

24 hours

Additional Information

• Number of Chapters: 36
• Number of Labs: 9
• Number of Demos: 2
• Current Version: 2023.1

What's New

• All labs updated to the latest software versions

Chapters

Chapter 1

• Introduction to Verilog

Chapter 2

• Verilog Keywords and Identifiers

Chapter 3

• Verilog Data Values and Number Representation

Chapter 4

• Verilog Data Types

Chapter 5

• Verilog Buses and Arrays

Chapter 6

• Verilog Modules and Ports

Chapter 7

• Verilog Operators

Chapter 8

• Continuous Assignment

Chapter 9

• Gate-Level Modeling

Chapter 10

• Procedural Assignment

Chapter 11

• Blocking and Non-Blocking Procedural Assignments

Chapter 12

• Procedural Timing Control

Chapter 13

• Verilog Control Structures: if-else

Chapter 14

• Verilog Control Structures: case

Chapter 15

• Verilog Loop Statements

Chapter 16

• Introduction to the Verilog Testbenches

Chapter 17

• System Tasks

Chapter 18

• Verilog Subprograms

Chapter 19

• Verilog Functions

Chapter 20

• Verilog Tasks

Chapter 21

• Verilog Compiler Directives

Chapter 22

• Verilog Parameters

Chapter 23

• Verilog Generate Statements

Chapter 24

• Timing Checks

Chapter 25

• Finite State Machines

Chapter 26

• Mealy Finite State Machines

Chapter 27

• Moore Finite State Machines

Chapter 28

• FSM Coding Guidelines – Verilog

Chapter 29

• Avoiding Race Conditions in Verilog

Chapter 30

• File I/O – Introduction

Chapter 31

• File I/O – Read Functions

Chapter 32

• File I/O – Write Functions

Chapter 33

• Targeting AMD FPGAs and Adaptive SoCs – Verilog

Chapter 34

• User-Defined Primitives (UDPs)

Chapter 35

• Programming Language Interface

Chapter 36

• Designing with Verilog Full Course Quiz