Advanced VHDL

Course Description

Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.



Training Duration

2 days

Who Should Attend?

VHDL users with introductory-to-intermediate knowledge of VHDL


  • Designing with VHDL course or equivalent knowledge of modeling, simulation, and RTL coding
  • At least 6 months of coding experience beyond an introductory course


  • Architecture: N/A*
  • Demo board: None*

* This course does not focus on any particular architecture.

Skills Gained

After completing this training, you will be able to:

  • Write efficient and reusable RTL, testbenches, and packages
  • Create self-testing testbenches
  • Create realistic models
  • Use the Text IO capabilities of the VHDL language
  • Store data dynamically
  • Create parameterized designs
  • Create parameterized code for design reuse

Course Outline

Day 1

  • Review of Current Knowledge
  • Simulation Concepts
  • Advanced Data Types
  • Subprograms and Design Attributes
  • Lab 1: Flexible Functions
  • Access Type Techniques and Blocks
  • Lab 2: Linked Lists with Access Types
  • Utilizing File IO
  • Lab 3: TextIO Techniques

Day 2

  • RTL Design and AMD Xilinx
  • Cool Stuff with VHDL
  • Lab 4: Creating Real-World Simulations
  • Supporting Multiple Platforms
  • Lab 5: Supporting Multiple Platforms
  • Non-Integer Numbers
  • Lab 6: Implementing Fixed and Floating Point Numbers
  • Course Summary

Lab Descriptions

  • Lab 1: Flexible Functions – Construct and use predefined attributes to build functions and procedures that automatically adjust to the size of the passed arguments as well as creating a reusable module with unconstrained ports.
  • Lab 2: Linked Lists with Access Types – Create linked lists to capture arbitrarily large data sets. Also included in this lab is a reusable helper package for managing singly linked lists.
  • Lab 3: TextIO Techniques – Load memory for synthesis via a text file using the TextIO extensions for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
  • Lab 4: Creating Real-World Simulations – Create spread-spectrum clocks with jitter and other real-world factors. Model board and behavioral component delay.
  • Lab 5: Supporting Multiple Platforms – Effectively use configuration statements, conditional generates, and scripts to build variations on VHDL themes.
  • Lab 6: Implementing Fixed and Floating Point Numbers – Construct a simple fixed point math example and compare to the IEEE_PROPOSED fixed and floating point models.

Event Schedule

so-logic (top1) (Austria)
  • 31.07. - 01.08.2024 09:00-17:00 — € 1,600.00 excl. VAT Add to cart
  • 30.10. - 31.10.2024 09:00-17:00 — € 1,600.00 excl. VAT Add to cart


Updated at: 2024-03-05 18:19:26 +0100to the top