Designing with VHDL

This course provides a thorough introduction to the VHDL language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and beha...

Course Description

This course provides a thorough introduction to the VHDL language. It covers writing efficient hardware designs, performing high-level HDL simulations, employing structural, register transfer level (RTL), and behavioral coding styles, targeting AMD devices and FPGA devices in general, and utilizing best coding practices.

The emphasis of this course is on:

• Writing efficient hardware designs
• Performing high-level HDL simulations
• Employing structural, RTL, and behavioral coding styles
• Targeting AMD devices and FPGA devices in general
• Utilizing best coding practices

Training Duration

27 hours

Additional Information

• Number of Chapters: 28
• Number of Labs: 11
• Number of Demos: 1
• Current Version: 2023.1

What's New

• Added new module: Vivado™ Simulator Good Coding Practices (VHDL)
• All labs updated to the latest software versions

Chapters

Chapter 1

• Introduction to VHDL

Chapter 2

• VHDL Design Units

Chapter 3

• VHDL Objects, Keywords, Identifiers

Chapter 4

• Scalar Data Types

Chapter 5

• Composite Data Types

Chapter 6

• VHDL Operators

Chapter 7

• Concurrency in VHDL

Chapter 8

• Concurrent Assignments

Chapter 9

• Processes and Variables

Chapter 10

• Control Structures in VHDL: if/else and case

Chapter 11

• Sequential Looping Statements

Chapter 12

• Delays in VHDL: Wait Statements

Chapter 13

• Introduction to the VHDL Testbench

Chapter 14

• VHDL Assert Statements

Chapter 15

• VHDL Attributes

Chapter 16

• Vivado Simulator Good Coding Practices (VHDL)

Chapter 17

• VHDL Subprograms

Chapter 18

• VHDL Functions

Chapter 19

• VHDL Procedures

Chapter 20

• VHDL Libraries and Packages

Chapter 21

• Interacting with the Simulation

Chapter 22

• Finite State Machine Overview – VHDL

Chapter 23

• Mealy Finite State Machine – VHDL

Chapter 24

• Moore Finite State Machine – VHDL

Chapter 25

• FSM Coding Guidelines – VHDL

Chapter 26

• Writing a Good Testbench

Chapter 27

• Targeting AMD FPGAs and Adaptive SoCs – VHDL

Chapter 28

• Designing with VHDL Full Course Quiz