Designing with System Verilog

En

Course Description

This comprehensive course is a thorough introduction to SystemVerilog constructs for design. This class addresses writing RTL code using the new constructs available in SystemVerilog. New data types, structs, unions, arrays, procedural blocks, re-usable tasks and functions, and packages, are all covered. The information gained can be applied to any digital design. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop RTL designs.

Release Date

January 2018

Level

FPGA 1

Training Duration

2 Days

Who Should Attend?

FPGA designers and logic designers

Prerequisites

Verilog design experience or completion of the Designing with Verilog course

Skills Gained

After completing this training, you will know how to:

  • Describe the features and benefits of using SystemVerilog for RTL design
  • Identify the new data types supported in SystemVerilog
  • Use an enumerated data type for coding a finite state machine (FSM)
  • Explain how to utilize structures, unions, and arrays
  • Describe the new procedural blocks and analyze the affected synthesis results
  • Define the enhancements and ability to reuse tasks and functions
  • Identify how to simplify module definitions and instantiations using interfaces
  • Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
  • Target and optimize Xilinx FPGAs by using SystemVerilog
  • Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
  • Download a complete SystemVerilog design to an evaluation board

Course Outline

Day 1

  • Introduction to SystemVerilog
  • Data Types
  • Lab 1: SystemVerilog Data Types
  • Structures, Unions, and Arrays
  • Additional Operators in System Verilog
  • Procedural Statements and Flow Control
  • Lab 2: always_ff and always_comb Procedural Blocks

Day 2

  • Functions, Tasks, and Procedures
  • Interfaces
  • Lab 3: Interfaces and Design Download
  • Packages
  • Targeting Xilinx FPGAs

Lab Descriptions

  • Lab 1: System Verilog Data Types – Utilize enumerated data types to build a finite state machine and perform synthesis to analyze the results.
  • Lab 2: always_ff and always_comb Procedural Blocks – Learn to use the new procedural blocks always_comb, always_ff, and always_latch to produce the synthesized results intended.
  • Lab 3: Interfaces and Design Download – Use an interface to simplify the module inputs and outputs. Download and verify the design in-circuit.

Event Schedule

so-logic (top1) (Austria)
  • 19.02. - 20.02.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 16.04. - 17.04.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 21.05. - 22.05.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 16.07. - 17.07.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 27.08. - 28.08.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 15.10. - 16.10.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
  • 03.12. - 04.12.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2018-11-11 14:08to the top