Designing with the Versal Adaptive SoC: Memory Interfaces

This course provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture, IP generation, simulation, and implementation are covered. Additional information on PCB...

Course Description

This course provides a system-level understanding of AMD Versal adaptive SoC memory interfaces. It covers memory controller architecture, IP generation, simulation, implementation, and PCB design issues.

The emphasis of this course is on:

• Constructing systems using Versal adaptive SoC external memory interfaces
• Selecting appropriate IP for applications
• Configuring memory controller IPs
• Using memory controllers in test benches and applications
• Simulating and implementing memory controller IPs
• Exploring traffic pattern generation
• Performance tuning for hardened DDRMC
• Accessing reference material for board design issues involving signal integrity, power supply, reference clocking, and trace design

Training Duration

19 hours

Additional Information

• Number of Chapters: 14
• Number of Labs: 7
• Number of Demos: 0
• Current Version: 2025.1

What's New

• New DDR5/LPDDR5 module with DDRMC5 content added
• New labs for DDRMC5 interface generation and simulation
• All labs updated to the latest software versions

Chapters

Chapter 1

• AMD Versal Adaptive SoC: Architecture Overview for Existing Users

Chapter 2

• AMD Versal Adaptive SoC: NoC Architecture

Chapter 3

• AMD Versal Adaptive SoC: Memory Solutions Overview

Chapter 4

• Versal Adaptive SoC – DDR4 and LPDDR4 Memories

Chapter 5

• DDR5 and LPDDR5 Memories

Chapter 6

• Versal Adaptive SoC – Hardened DDR Memory Controllers

Chapter 7

• Versal Adaptive SoC – Configuring the Hardened DDR Memory Controllers

Chapter 8

• Versal Adaptive SoC – Simulating the Hardened DDR Memory Controllers

Chapter 9

• Versal Adaptive SoC – Implementing the Hardened DDR Memory Controllers

Chapter 10

• Versal Adaptive SoC – DDRMC Performance Tuning

Chapter 11

• Versal Adaptive SoC – Debugging the Memory Interfaces

Chapter 12

• Versal Adaptive SoC – DDR4 Soft Controller

Chapter 13

• Versal Adaptive SoC – Memory Interfaces PCB Design

Chapter 14

• Designing with the Versal Adaptive SoC: Memory Interfaces Full Course Quiz