Designing with the Versal Adaptive SoC: Design Methodology

Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and ther...

Course Description

This course teaches AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. It covers embedded software development, AI Engine development, system design planning, power estimation, RTL flows, timing closure, configuration, debugging, system performance improvements, and system-level simulation.

The emphasis of this course is on:

• Demonstrating the embedded software development flow for Versal devices
• Demonstrating the AI Engine development flow
• Using provided design tools and methodologies to create complex systems
• Leveraging the Power Design Manager (PDM) tool for power estimation
• Identifying adaptive SoC power and thermal solutions
• Enabling top-level RTL flows for Versal devices
• Applying common timing closure techniques
• Performing device configuration and debugging
• Improving Versal adaptive SoC system performance
• Performing system-level simulation

Training Duration

32 hours

Additional Information

• Number of Chapters: 23
• Number of Labs: 11
• Number of Demos: 0
• Current Version: 2025.2

What's New

• Added techniques for reducing clock skew in AMD Versal devices within the Versal Timing Closure Techniques module
• Added information on SLR crossing report within the Optimizing SLR Crossings in SSI Technology module
• Added new labs: Linux Application Development using the Embedded Development Framework (EDF) & Segmented Configuration for AMD Versal devices
• All labs updated to the latest software versions

Chapters

Chapter 1

• AMD Versal Adaptive SoC: Embedded Software Development

Chapter 2

• Using the AMD Embedded Development Framework

Chapter 3

• Introduction to the Software Hardware Exchange Loop (SHEL) Flow

Chapter 4

• AMD Versal Adaptive SoC: Software Stack

Chapter 5

• AI Engine Programming – Kernels and Graphs

Chapter 6

• AMD Versal Adaptive SoC: System Design Planning Methodology

Chapter 7

• AMD Versal Adaptive SoC: AI Engine System Partitioning

Chapter 8

• AMD Versal Adaptive SoC: Power Design Manager

Chapter 9

• AMD Versal Adaptive SoC: Power and Thermal Solutions

Chapter 10

• AMD Versal Adaptive SoC: Hardware, IP, and Platform Development Methodology

Chapter 11

• AMD Versal Adaptive SoC: Enabling Top-level RTL Flows

Chapter 12

• AMD Versal Adaptive SoC: Timing Closure Overview

Chapter 13

• AMD Versal Adaptive SoC: Timing Closure Techniques

Chapter 14

• Optimizing SLR Crossings in SSI Technology Introduction

Chapter 15

• AMD Versal Adaptive SoC: Board System Design Methodology

Chapter 16

• AMD Versal Adaptive SoC: Security Management and Safety Features

Chapter 17

• AMD Versal Adaptive SoC: System Integration and Validation Methodology

Chapter 18

• AMD Versal Adaptive SoC: Configuration and Debugging

Chapter 19

• AMD Versal Adaptive SoC: Segmented Configuration

Chapter 20

• AMD Versal Adaptive SoC: Overview of HSDP

Chapter 21

• AMD Versal Adaptive SoC: Fabric Debug

Chapter 22

• AMD Versal Adaptive SoC: System Simulation

Chapter 23

• Designing with the Versal Adaptive SoC: Design Methodology Full Course Quiz