Designing with the UltraScale and UltraScale+ Architectures

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Course Description

This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ and UltraScale+™ architectures. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered. In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

Release Date

April 2016

Level

FPGA 3

Training Duration

2 days

Who Should Attend?

Anyone who would like to build a design for the UltraScale device family.

Prerequisites

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:
  • Take advantage of the primary UltraScale architecture resources
  • Describe the new CLB capabilities and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO, and DSP resources available
  • Describe the UltraRAM features
  • Properly design for the I/O and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included
  • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1

  • UltraScale Architecture Overview
  • UltraScale+ Families Overview
  • Design Migration Software Recommendations
  • CLB Architecture and HDL Coding Styles
  • Lab 1: Optimal Coding Styles for CLB Resources
  • Clocking Resources
  • Lab 2: Clocking Migration
  • Lab 3: Clocking Resources
  • Memory Resources
  • Lab 4: DDR3 MIG Design Migration
  • Lab 5: DDR4 MIG Design Creation

Day 2

  • DSP Resources
  • I/O Resources
  • Lab 6:SelectIO Design (Component Mode)
  • FPGA Design Migration
  • Design Migration Case Study
  • Lab 7: QSGMII Design Migration
  • Lab 8: 10G PCS/PMA and MAC Design Migrationv
  • Demo: Transceiver Wizard
  • Transceiver Overview
  • Lab 9: Transceiver Core Resources
  • Lab Descriptions

    • Lab 1: Optimal Coding Styles for CLB Resources – Analyze a design that has asynchronous resets by generating various reports such as the Timing Summary report and Utilization report. Convert the asynchronous resets to synchronous resets by removing the reset signal from the sensitivity list. Also examine the CLB resources, such as the LUT and the dedicated carry chain.
    • Lab 2: Clocking Migration – Migrate a 7 series design to the UltraScale architecture with a focus on clocking resources.
    • Lab 3:Clocking Resources ndash; Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.
    • Lab 4: DDR3 MIG Design Migration – Migrate a 7 series MIG design to the UltraScale architecture. The provided MIG design was targeted to a Kintex® UltraScale device (KC705 evaluation board) with DDR3 memory on board. In this case, the design will be migrated to use an UltraScale DDR3 memory interface.
    • Lab 5: DDR4 MIG Design Creation – Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility.
    • Lab 6:SelectIO Design (Component Mode) – Implement a high-performance, source-synchronous interface using the UltraScale architecture SelectIO in Component mode.
    • Lab 7: QSGMII Design Migration – Migrate an existing 7 series QSGMII example design to a Kintex UltraScale architecture-based device. This lab will show you how to update your port connections and use the optimum logic resources available.
    • Lab 8: 10G PCS/PMA and MAC Design Migration – Migrate a successfully implemented 7 series design containing 10G Ethernet MAC and 10G PCS/PMA IP to an UltraScale FPGA.
    • Lab 9: Transceiver Core Resources – Use the Transceiver Wizard to build a design that uses a single serial transceiver and observe the file structures created.

    Event Schedule

    so-logic (top1) (Austria)
    • 15.01. - 16.01.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
    • 05.03. - 06.03.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
    • 23.04. - 24.04.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
    • 04.06. - 05.06.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
    • 30.07. - 31.07.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
    • 10.09. - 11.09.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart
    • 28.10. - 29.10.2019 09:00-17:00 — € 1,500.00 excl. VAT Add to cart

    Partner

    Xilinx
    Updated at: 2016-08-03 09:26to the top