Designing with the UltraScale and UltraScale+ Architectures

Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...

Course Description

This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. It covers CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. The course also describes improvements to dedicated transceivers and the Transceiver Wizard, reviews the Memory Interface Generator (MIG) and DDR4 memory interface capabilities, and explains how to migrate existing designs and IP to the UltraScale architecture using the Vivado™ Design Suite.

The emphasis of this course is on:

• Introducing CLB resources, clock management resources, global and regional clocking resources, memory and DSP resources, and source-synchronous resources
• Describing improvements to dedicated transceivers and the Transceiver Wizard
• Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
• Migrating existing designs and IP to the UltraScale architecture using the Vivado Design Suite

Training Duration

27 hours

Additional Information

• Number of Chapters: 16
• Number of Labs: 13
• Number of Demos: 2
• Current Version: 2024.2

What's New

• All labs have been updated to the latest software versions

Chapters

Chapter 1

• Introduction to the UltraScale Architecture

Chapter 2

• AMD UltraScale Architecture CLB Resources

Chapter 3

• HDL Coding Techniques

Chapter 4

• AMD UltraScale Architecture Clocking Resources

Chapter 5

• FPGA Design Migration

Chapter 6

• AMD UltraScale Architecture Block RAM Memory Resources

Chapter 7

• AMD UltraScale Architecture FIFO Memory Resources

Chapter 8

• UltraRAM Memory

Chapter 9

• High Bandwidth Memory

Chapter 10

• AMD UltraScale Architecture DSP Resources

Chapter 11

• Design Migration Software Recommendations

Chapter 12

• AMD UltraScale Architecture I/O Resources: Component Mode

Chapter 13

• Design Migration Methodology

Chapter 14

• AMD UltraScale Architecture Transceivers

Chapter 15

• Introduction to the AMD UltraScale+ Families

Chapter 16

• Designing with the UltraScale and UltraScale+ Architectures Full Course Quiz