8051 Microcontroller Cores

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Index

General Description
CPU Features
Peripherals
Applications
Deliverables
Licensing
Datasheets
Evaluation Models
Pricing and Additional Information

General Description

The So-Logic 8051 cores are soft cores of a single-chip 8-bit embedded microcontroller dedicated for operation with fast (on-chip) and slow (off-chip) memories. Currently there are two different 8051 microcontroller cores offered by the So-Logic:

  • so_ip_8051M256 Microcontroller Core - complete 8051 microcontroller (with two timers and one UART), with 256 bytes of internal RAM

  • so_ip_8051C256 Microcontroller Core - 8051 CPU core without peripheral units (two timers and one UART), with 256 bytes of internal RAM

For more information about the differences between the cores please consult the corresponding datasheet.

Each core is 100% binary compatible with the industry standard 8051 microcontroller. It executes all ASM51 instructions and has the same instruction set as the 8031. The cores serve both software and hardware interrupts, and have standard peripheral units like timers and serial communication system.

Cores have an advanced architecture that enables them to be 4.51 times faster than the original 8051 microcontroller.

All cores are delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow. Each core has microcode-free design developed for reuse in FPGA implementations. Design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.

CPU Features

100% software compatible with industry standard 8051

  • Advanced architecture enables to execute instructions on average 4.51 times faster compared to original 8051
  • 8 times faster multiplication
  • 8 times faster division
  • 4 times faster addition
  • 256 bytes of internal (on-chip) Data Memory
  • Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
  • Up to 64K bytes of internal (on-chip) or external (off-chip) Data Memory
  • De-multiplexed Address/Data bus to allow easy connection to memory
  • Fully synthesizable synchronous design with positive edge clocking and no internal tri-state

Peripherals

Interrupt Controller

  • 2 priority levels
  • 2 external sources
  • 3 internal sources from peripherals

Four 8-bit I/O Ports

  • Separate input and output lines
  • Alternate port functions such as interrupts and serial interface are separated, providing extra port pins in comparison with original 8051

Two 16-bit timer/counters

  • Timers clocked by internal source
  • Auto reload 8-bit timers
  • Externally gated event counters

Full-duplex serial port

  • Synchronous mode, fixed baud rate
  • 8-bit asynchronous mode, variable baud rate
  • 9-bit asynchronous mode, fixed baud rate
  • 9-bit asynchronous mode, variable baud rate

Applications

  • Embedded microcontroller systems
  • Data computation and transfer
  • Communication systems
  • Professional audio and video

Deliverables

Source code (source code license only)

  • VHDL Source Code

VHDL test bench environment

  • Tests with reference responses

Technical documentation

  • Installation notes
  • HDL core specification
  • Datasheet

Instantiation templates

Example application

Technical Support

  • IP Core implementation support
  • Variable length maintenance
  • Delivery of IP Core updates, minor and major changes
  • Delivery of documentation updates
  • Telephone & email support

Licensing

Netlist License

  • Post-synthesis netlist
  • Self checking testbench
  • Test vectors for testing the core
  • Place&Route scripts
  • Constraints
  • Instantiation templates
  • Documentation

VHDL Source License

  • VHDL RTL source code
  • Complete verification plan together with testbenches needed to verify correct operation of the core
  • Self checking testbench
  • Vectors for testing the functionality of the core
  • Simulation & synthesis scripts
  • Documentation

Datasheets

For more information about the So-Logic 8051 cores, please see the following datasheets:

Evaluation Models

Evaluation models for each core is avaiable upon the request. Evaluation model is fully functional and synthesizable, but it has time limited operation. Using this model, customer can evaluate the functionality and performance of the core in target system for limited period of time. For more information about the evaluation model, please contact So-Logic at ip_8051@so-logic.net.

Pricing and Additional Information

Pricing of 8051 cores varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the 8051 cores, please contact So-Logic at:

Phone: +43-1-315 77 77-11
Fax:     +43-1-315 77 77-44
email:  ip_8051@so-logic.net

Updated at: 2011-01-16 09:52to the top