Designing with Virtex-4 Family

Interested in learning how to utilize Virtex™-4 FPGA architectural resources effectively? This course focuses on understanding as well as utilizing several of the new and enhanced resources found in our newest device. Topics covered include an overview of the Virtex-4 FPGA; the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD); global and regional clocking techniques, memory and FIFO; and source synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course.

Level

Intermediate

Training Duration

2 days

Who Should Attend?

Experienced Xilinx users or those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. Students should have a solid understanding of Virtex-II, Virtex-II Pro, and Virtex-II ProX FPGA architectures, the ISE™ software, timing constraints, and timing closure techniques.

Prerequisites

• Fundamentals of FPGA Design course
• Designing for Performance course
• Understanding of the Virtex-II, Virtex-II Pro, and Virtex-II ProX FPGA architecture
• Intermediate knowledge of VHDL or Verilog

Software Tools

• Xilinx ISE
• Xilinx XST

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Utilize Virtex-4 FPGA global clocking resources
• Utilize Virtex-4 FPGA regional clocking resources
• Design with the Virtex-4 FPGA DCM
• Design the Virtex-4 FPGA PMCD
• Discuss Virtex-4 FPGA block RAM and FIFO blocks
• Utilize the DSP48 block
• Explain source-synchronous resources

Course Outline

Day 1

• Introduction
• Product Overview
• DCM Clock Management
• PMCD Clock Management
• Lab 1: DCM Clocking
• Clock Networks
• Lab 2: Clocking Resources

Day 2

• Day 2 Overview
• I/O and Source-Synchronous Resources
• Lab 3: Utilizing Source-Synchronous I/O Resources
• Block RAM Memory Resources
• FIFO16 Memory Resources
• Lab 4: Utilizing Block RAM and FIFO16
• XtremeDSP™ Technology Slice
• Lab 5: Utilizing XtremeDSP Technology Resources
• Configuration
• Day 2 Review

Lab Descriptions

• Lab 1 - DCM Clocking: Designing a clock management scheme with DCMs and PMCDs
• Lab 2 - Clocking Resources: Utilizing global and regional clock networks
• Lab 3 - Utilizing Source-Synchronous I/O Resources: Creating a source-synchronous design interface for a network application
• Lab 4 - Utilizing Block RAM and FIFO16: Utilizing new block RAM features and FIFO16 dedicated resources
• Lab 5 - Utilizing XtremeDSP Technology Resources: Utilizing the DSP48 block