SystemC Concepts



SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog, but is more aptly described as a system-level modeling language.

SystemC is applied to system-level modeling, architectural exploration, performance modeling, software development, functional verification, and high-level synthesis. SystemC is often associated with Electronic system level (ESL) design, and with Transaction-level modeling (TLM).

SystemC is defined and promoted by OSCI, the Open SystemC Initiative, and has been approved by the IEEE Standards Association as IEEE 1666-2005, the SystemC Language Reference Manual (LRM). The LRM provides the definitive statement of the semantics of SystemC. OSCI also provide an open-source proof-of-concept simulator (sometimes incorrectly referred to as the reference simulator), which can be downloaded from the OSCI website. Although it was the intent of OSCI that commercial vendors and academia could create original software compliant to IEEE 1666, in practice most SystemC implementations have been at least partly based on the OSCI proof-of-concept simulator.

SystemC has semantic similarities to VHDL and Verilog, but may be said to have a syntactical overhead compared to these when used as a hardware description language. On the other hand, it offers a greater range of expression, similar to object oriented design partitioning and template classes. Although strictly a C++ class library, SystemC is sometimes viewed as being a language in its own right. Source code can be compiled with the SystemC library (which includes a simulation kernel) to give an executable. The performance of the OSCI open-source implementation is typically less optimal than commercial VHDL/Verilog simulators when used for register transfer level simulation.

SystemC version 1 included common hardware description language features such as structural hierarchy and connectivity, clock cycle accuracy, delta cycles, 4-state logic (0, 1, X, Z), and bus resolution functions. From version 2 onward, the focus of SystemC has moved to communication abstraction, transaction-level modeling, and virtual platform modeling. SystemC version 2 added abstract ports, dynamic processes, and timed event notifications.

Training Duration

3 days

Who Should Attend?

FPGA designers interested in FPGA design high level system description for verification and implementation


  • Programming Skills in C/C++
  • Intermediate HDL knowledge (VHDL or Verilog)
  • Solid digital design background

Course Description

  • Ideas
  • Tools
  • Modeling
  • Modules and Hierarchy
  • Process and Time
  • Ports and Signals
  • Channel and Interfaces
  • Data types
  • VHDL, Verilog Design Guide
  • Available Libraries
  • SystemC TLM Transaction Level Modeling
  • SystemC SV System Verification
  • SystemC ASM Analog System Modeling
  • Crystal Ball


  • Hello World
  • Design Hierachy Pipeline
  • Filters
  • FFT
  • Modulator
  • Channels

Event Schedule

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Updated at: 2011-12-27 16:00to the top