Xilinx - Vivado Adopter Class (Live Online)

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Course description:

The training uses materials developed by Xilinx, and conveniently combines:
  • Vivado Design Suite
  • Xilinx Vivado Advanced STA and XDC
  • UltraFast Design Methodology
  • Who should attend?

    FPGA designers looking to utilize Vivado who:
    • currently use the Xilinx ISE Design Suite
    • already have some familiarity with Xilinx 7-Series devices

    PLEASE NOTE: Engineers who are unfamiliar with Xilinx devices with no prior Xilinx ISE Design Suite experience should attend Vivado FPGA Essentials. This course provides new users a good grounding before attending more advanced training. See the learning path above and please contact Doulos for further information.

    Pre-requisites

    • FPGA design experience
    • Intermediate VHDL or Verilog knowledge
    • Completion of the Vivado FPGA Essentials or Essentials and Design for Performance and Advanced FPGA Implementation courses, or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques.
    • Video Resources. The following videos contain essential content that will enable you to maximise the effectiveness of the Vivado training course:
    • Essential viewing prior to course attendance: http://www.xilinx.com/training/vivado/vivado-design-flows-overview.htm
    • Optional viewing prior to course attendance: http://www.xilinx.com/training/vivado/vivado-version-control-overview.htm

    Recommended additional training

    • Essential Tcl for Vivado (online) teaches the essentials of the Tcl language with particular focus on its application within the Xilinx Vivado™ Design Suite*. It can be taken independently either before or after Vivado Adopter training as convenient (subject to availability).

    Skills gained

    After comlpeting this course you will be able to:

    Vivado Design Suite

    • Use the Project Manager to start a new project
    • Identify the Vivado IDE design flows (project based and non-project batch)
    • Identify file sets (HDL, XDC, simulation)
    • Analyze designs using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
    • Synthesize and implement an HDL design
    • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
    • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)

    Xilinx Vivado Advanced XDC and STA

    • Access primary objects from the design database and filter lists of objects using properties
    • Describe setup and hold checks and describe the components of a timing report
    • Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
    • Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
    • Describe all of the options available with the report_timing and report_timing_summary commands
    • Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
    • Analyze a timing report to identify how to center the clock in the data eye
    • Create scripts for the project-based and non-project batch design flows.

    UltraFast Design Methodology

    • Describe the UltraFast Design Methodology Checklist
    • Identify key areas to optimize your design to meet your design goals and performance objectives
    • Define a properly constrained design
    • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
    • Build resets into your system for optimum reliability and design speed
    • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
    • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
    • Identify timing closure techniques using the Vivado Design Suite
    • Describe how the Xilinx design methodology techniques work effectively through case study/lab experience

    Registration and further information

    You can find further information and register for this course at the homepage of our partner here

Event Schedule

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Updated at: 2016-01-15 12:03to the top