Xilinx - Vivado FPGA Essentials (Online)

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(Also known as Essentials of FPGA Design by Xilinx)

Course Description

This course will enable you to:
  • build an effective FPGA design using synchronous design techniques
  • instantiate appropriate device resources
  • use proper HDL coding techniques
  • make good pin assignments
  • set basic XDC constraints
  • use the Vivado Design Suite to build, synthesize, implement, and download a design.

Who Should Attend?

  • Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
  • Existing Xilinx ISE users who have no previous experience or training with the Xilinx PlanAhead suite and little or no knowledge of Kintex-7 or Virtex-7 devices.
  • Engineers wishing to design with 6-series devices should contact Doulos for further information.
  • Engineers who are already familiar with Xilinx 7-series devices and have at least some familiarity with PlanAhead should instead attend Vivado Design Suite. See the recommended learning path above and please contact Doulos for further information.

Prerequisites

  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience

Skills Gained

After completing this training, you will know how to:
  • Take advantage of the primary 7 series FPGA architecture resources
  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Build custom IP with the IP Library utility
  • Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
  • Describe and analyze common STA reports
  • Identify synchronous design techniques
  • Describe how an FPGA is configured.

Registration and further information

You can find further information and register for this course at the homepage of our partner here

Event Schedule

No events found. Event request.

Partner

Doulos
Updated at: 2016-01-15 11:57to the top