Versal Compendium 1 : Architecture

Each day with a lot of presentation and demonstration all virtual on your screen!

  • Reviewing the architecture of the Versal ACAP
  • Describing the different engines available in the Versal architecture and what resources they contain
  • Utilizing the hardened blocks available in the Versal architecture
  • Using the design tools and methodology provided by Xilinx to create complex systems
  • Performing system-level simulation and debugging

Agenda



  • 9:00 - 10:30 Overview Architecture and Sub Families
  • 10:45 - 12:15 Design Flow and Tools (Simulation, Emulation, Debugging, Profiling)
  • 13:00 - 14:30 Processing System PS
  • 14:45 -16:15 Adaptable Engine (Programmable Logic PL)
  • 16:15 Q&A

Event Schedule

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Updated at: 2021-08-18 22:47:04 +0200to the top