Designing with Spartan-6 and Virtex-6 Families

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Course Description

Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.

Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.

This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.

Release Date

March 2011

Level

FPGA 3

Training Duration

3 days

Who Should Attend?

For those who have taken the Essentials of FPGA Design course.

Prerequisites

Software Tools

Xilinx ISE® Design Suite: Logic or System Edition

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the Spartan-6 and Virtex-6 FPGAs
  • Specify the CLB resources and the available slice configurations for the Spartan-6 and Virtex-6 FPGAs
  • Define the block RAM and DSP resources available for Spartan-6 and Virtex-6 FPGAs
  • Properly design for the I/O block and SERDES resources
  • Identify the DCM, PLL, and clock routing resources included with each of these families
  • Identify the supported memory controllers for the Spartan-6 and Virtex-6 FPGAs
  • Properly code your HDL to get the most out of these devices
  • Describe the additional dedicated hardware for all the Spartan-6 and Virtex-6 families

Course Outline

Day 1

  • Spartan-6 FPGA Overview
  • Virtex-6 FPGA Overview
  • CLB Resources
  • Lab 1: CLB Resources
  • Spartan-6 and Virtex-6 FPGA Memory Resources
  • Spartan-6 and Virtex-6 FPGA DSP Resources

Day 2

  • Lab 2: DSP Resources
  • Basic I/O Resources
  • Spartan-6 FPGA I/O Resources
  • Virtex-6 FPGA I/O Resources
  • Basic Clocking Resources
  • Spartan-6 FPGA Clocking Resources

Day 3

  • Virtex-6 FPGA Clocking Resources
  • Lab 3: Clocking Resources
  • Spartan-6 and Virtex-6 FPGA Memory Controllers
  • HDL Coding Techniques
  • Lab 4: HDL Coding Techniques
  • Dedicated Hardware in the Spartan-6 and Virtex-6 FPGAs

Lab Descriptions

  • Lab 1: CLB Resources – Gain comprehensive experience with the CLB architecture. Synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
  • Lab 2: DSP Resources – Using XST, synthesize and implement a 24x17 MAC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.
  • Lab 3: Block RAM Resources – Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.
  • Lab 4: HDL Coding Techniqus – Using XST, synthesize various components into the design and evaluate the impact that proper HDL coding techniques have on the size and speed of implementation results.

Event Schedule

No events found. Event request.

Partner

Xilinx
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