Spartan-6 with ISE Migration to 7 Series with Vivado

Three workshops each one day long, one day each week

Course Outline day 1



  • Targeting/Retargeting Considerations for 7 Series Devices
  • HDL Coding Considerations
  • Use of DSP and Other Arithmetic Intensive Code
  • RAM Consideration
  • Use of Synthesis and Physical Constraints
  • Software Options
  • Use of LUTs as Route-Thrus

Course Outline day 2



  • Virtex-6 FPGA
  • Re-Targeting Considerations
  • Introduction
  • 7 Series DeviceSelection
  • Use of Existing SoftIP
  • EDIF,or NGC Netlists
  • Clocking Considerations
  • Driving Non-Clock Loads with GlobalBuffers
  • Other Primitive Retargeting Considerations
  • Using Unimacros
  • I/OConsiderations
  • XilinxResources
  • SolutionCenters
  • Documentation Navigator and DesignHubs
  • TrainingResources
  • VivadoDocumentation

Course Outline day 3



  • Practice lets look at you designs!!

Event Schedule

so-logic (top1) (Austria)
  • 22.02. - 24.02.2022 09:00-17:00 — € 0.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2022-01-14 05:53:36 +0100to the top