Designing with the Versal ACAP: Network on Chip

Course Description

This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device. The emphasis of this course is on:

  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement

Release Date

January 2022

Training Duration

1 day

Who Should Attend?

Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices

Prerequisites

  • Any Xilinx device architecture class
  • Familiarity with the Vivado® Design Suite

Skills Gained

After completing this comprehensive training, you will know how to:

  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement

Course Outline



  • Architecture Overview for Existing Xilinx Users
  • Versal ACAPs Compared to Zynq UltraScale+ Devices/li>
  • Versal ACAPs: NoC Introduction and Concepts
  • Versal ACAPs: NoC Architecture
  • Versal ACAPs: Design Tool Flow (NOC)
  • Versal ACAPs: NoC DDR Memory Controller
  • Versal ACAPs: NoC Performance Tuning
  • Versal ACAPs: System Design Migration
  • Designing with the Versal ACAP: Network on Chip Full Course Quiz

Event Schedule

so-logic (top1) (Austria)
  • 06.02. - 06.02.2023 09:00-17:00 — € 800.00 excl. VAT Add to cart
  • 17.05. - 17.05.2023 09:00-17:00 — € 800.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2022-07-04 12:38:49 +0200to the top