Designing with the Versal ACAP: Architecture and Methodology

Course Description

In this course you will learn about Versal™ ACAP architecture and design methodology. The emphasis of this course is on:

  • Reviewing the architecture of the Versal ACAP
  • Describing the different engines available in the Versal architecture and what resources they contain
  • Utilizing the hardened blocks available in the Versal architecture
  • Using the design tools and methodology provided by Xilinx to create complex systems
  • Describing the network on chip (NoC) and AI Engine concepts and ther architectures
  • Performing system-level simulation and debugging

Release Date

January 2022


Connectivity 3

Training Duration

4 days

Who Should Attend?

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device


  • Comfort with the C/C++ programming language
  • Vitis™ IDE software development flow
  • Hardware development flow with the Vivado® Design Suite
  • Basic knowledge of UltraScale™/UltraScale+™ FPGAs and Zynq® UltraScale+ MPSoCs

Course Outline

  • Versal ACAP: Introduction
  • Versal ACAP: Architecture Overview
  • Versal ACAP: Design Tool Flow
  • Versal ACAP: Adaptable Engines (PL)
  • Versal ACAP: Processing System
  • Versal ACAP: PMC and Boot and Configuration
  • Versal ACAP: SelectIO Resources
  • Versal ACAP: Clocking Architecture
  • Versal ACAP: System Interrupts
  • Versal ACAP: Timers, Counters, and RTC
  • Versal ACAP: Software Build Flow
  • Versal ACAP: Software Stack
  • Versal ACAP: DSP Engine
  • Versal ACAP: AI Engine
  • Versal ACAP: NoC Introduction and Concepts
  • Versal ACAP: Device Memory
  • Versal ACAP: Programming Interfaces
  • Versal ACAP: Application Partitioning
  • Versal ACAP: PCI Express & CCIX
  • Versal ACAP: Serial Transceivers
  • Versal ACAP: Power and Thermal Solutions
  • Versal ACAP: Debugging
  • Versal ACAP: Security Features
  • Versal ACAP: System Simulation
  • Versal ACAP: System Design Methodology
  • Versal ACAP: Hardware, IP, and PLatform Development Methodology
  • Versal ACAP: System Integration and Validation Methodology
  • Designing with the Versal ACAP: Architecture and Methodology Full Course Quiz

Event Schedule

so-logic (top1) (Austria)
  • 07.02. - 10.02.2023 09:00-17:00 — € 3,200.00 excl. VAT Add to cart
  • 09.05. - 12.05.2023 09:00-17:00 — € 3,200.00 excl. VAT Add to cart


Updated at: 2022-07-04 12:40:26 +0200to the top