Designing with Versal AI Engine 1 - Architecture and Design Flow

Course Description

This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features.

Training Duration

2 days

Who Should Attend?

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the AMD Xilinx Versal AI Engine

Skills Gained

After completing this comprehensive training, you will know how to:

  • Illustrating the AI Engine architecture
  • Designing single AI Engine kernels using the Vitis™ unified software platform
  • Designing multiple AI kernels using data flow graphs with the Vitis IDE
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
  • Analyzing and debugging kernel performance

Course Outline

  • Overview of Versal Adaptive SoC Architecture
  • Introduction to the AI Engine Architecture
  • Versal AI Engine Memory and Data Movement
  • Versal Adaptive SoC Tool Flow
  • Application Partitioning on Versal Adaptive SoC 1
  • Scalar and Vector Datatypes
  • Intrinsic Functions
  • Window and Streaming Data APIs
  • Vitis Analyzer
  • The Programming Model - Single Kernel
  • The Programming Model - Single Kernel Using Vector Data Types
  • The Programming Model - Introduction to the Adaptive Data Flow (ADF) Graph
  • The Programming Model: Multi Kernel Using Graph
  • Designing with Versal AI Engine 1 Full Course Quiz

Event Schedule

so-logic (top1) (Austria)
  • 02.09. - 03.09.2024 09:00-17:00 — € 1,600.00 excl. VAT Add to cart
  • 02.12. - 03.12.2024 09:00-17:00 — € 1,600.00 excl. VAT Add to cart


Updated at: 2024-03-04 17:49:45 +0100to the top