Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment

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Course Description

This OnDemand course focuses on using the Xilinx tools to accelerate a design at the system architecture level and optimize the accelerators. This course is for people who want to develop new or existing OpenCL™, C/C++, and RTL applications in the SDAccel™ development environment, for use on Xilinx FPGAs. The course also includes an introduction to targeting the Alveo™accelerator card. After completing this course, you will be able to: debug and profile OpenCL API code using the SDAccel development environment, maximize performance, efficiently utilize FPGA resources, utilize memory techniques to reduce latency, utilize the massive parallelism inherent to FPGAs, optimize throughput, and pipeline for performance.

Release Date

November 2018

Level

Training Duration

Who Should Attend?

Prerequisites

Skills Gained

After completing this comprehensive training, you will know how to:

  • Introduction to the SDAccel Environment and OpenCL Framework
  • SDAccel Environment - SDAccel Tool Overview
  • Introduction to FPGAs
  • Host Code - Open CL Execution Model
  • Profiling
  • Optimization Methodologies
  • Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators
  • C Based Kernels
  • C Based Kernel Optimization
  • Setting up Alveo U200 Accelerator Card for SDAccel

Course Outline

Lab Descriptions

Event Schedule

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Updated at: 2018-11-11 13:11to the top